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- Path: sparky!uunet!olivea!sgigate!odin!mash.wpd.sgi.com!mash
- From: mash@mash.wpd.sgi.com (John R. Mashey)
- Newsgroups: comp.arch
- Subject: Re: 100 Mips Intel NeXT (processor comparison)
- Message-ID: <1993Jan6.015458.7674@odin.corp.sgi.com>
- Date: 6 Jan 93 01:54:58 GMT
- References: <1992Dec24.190008.25875@ohsu.edu> <BzvJys.CwD@cs.mcgill.ca> <1992Dec31.013141.132685@zeus.calpoly.edu> <1992Dec31.022317.17674@wam.umd.edu>
- Sender: news@odin.corp.sgi.com (Net News)
- Organization: Silicon Graphics, Inc.
- Lines: 22
- Nntp-Posting-Host: mash.wpd.sgi.com
-
- In article <1992Dec31.022317.17674@wam.umd.edu>, rsrodger@wam.umd.edu (Yamanari) writes:
- |> In article <1992Dec31.013141.132685@zeus.calpoly.edu> mneideng@thidwick.acs.calpoly.edu (Mark Neidengard) writes:
- |> >I think that the way of getting around this bottleneck is to use EXTENSIVE
-
-
- |> >Don't be surprised if CPU's start coming out with 1 meg of onboard cache
- |> >within the next year...
- |>
- |>
- |> Is this really likely, given the complexity (according to
- |> net rumor) already involved in fabricating the Alpha?
-
- There are already reasonable numbers of *workstations* out there with 1MB
- of cache on the motherboards (i.e., SGI Crimsons, in 1Q92; MIPS Magnums
- & Milleniums; SGI Indigo 4000s; Sun SS10-41s (just recently); etc.
-
- If the comment meant 1MB of cache on the CPU chip, expect to wait a while....
-
- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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