NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/sys/ibm/pc/hardware/34497

Text File | 1992-12-31 | 3.0 KB | 54 lines

Newsgroups: comp.sys.ibm.pc.hardware
Path: sparky!uunet!cs.utexas.edu!asuvax!chnews!hfglobe!ptd!ssivakum
From: [e-mail] (Sam Sivakumar)
Subject: Re: What's the deal? My chip says "SX-25"; Norton says "SX-33"
Message-ID: <[e-mail]>
Organization: Intel Corporation -- Aloha, Oregon
References: <[e-mail]> <[e-mail]>
Date: Thu, 31 Dec 1992 02:21:46 GMT
Lines: 43

In article <[e-mail]> [e-mail] (Matthias Kamm) writes:
>:
>: The usual route is exactly as Danny had stated: test every part at 33MHz.
>: If it fails, test it at 25.  If it fails, keep going down until you are
>: out of speed.
>
>This is very possibly wrong.  If this were the case, then the cost of test for
>the 16Mhz chip would be three times that of the 33Mhz chip (assuming 33,25,16
>speed grades for their microprocessors).

    Any and all metrology (CD or film thickness measurements during the
fabrication process, as well as testing) are non-value-added steps.  So, we
are constantly under pressure to either improve the control of our process,
which would enable us to eliminate some of these measurements or otherwise
to at least decrease the time it takes for measurements.
    As I said in an earlier posting, I do not work in sort/test, but
I am frequently referring to their reports on wafer lots that we processed
through the line.  A single test is done that skews both voltage and speed
while monitoring functionality.  Thus, at the end of the test, every chip
on the wafer is "binned" into a speed category or inked indicating failure.
    It must also be borne in mind that chip manufacturers have various
process lines in operation at the same time.  Apart from the familiar
distinctions like a 1 um CMOS process, or a 0.8 um HCMOS process, or a
0.5 um BiCMOS process, each process can also have sub-processes that have
slightly different gate lengths.  There is usually some flexibility in
trading off process margins in the fab (leading to lower yields, possibly)
for smaller device features while still using the same process.  Some of
these techniques can be used by manufacturers to offer slightly enhanced
versions of the vanilla products that came out earlier.
    If anyone has any specific questions on how an IC manufacturing
line is run in practice, I would be happy to answer them to the best of
my ability.  Without attemting to sound like an Intel spokesman, I can say
that we do test the heck out of the chips that leave our factories.  While
we may use statistical sampling to check for example, the metal film thickness
on a batch of wafers in the line, EVERY individual chip undergoes electrical
testing.
    By the way, much or all of what I said above applies to just about
any reputable semiconductor manufacturer in the world.

--
Sam Sivakumar            |  Intel's very own lithography dude,
[e-mail]   |  Speakin' for himself, that's for sure!
PTD, Aloha, OR              |