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- Path: sparky!uunet!charon.amdahl.com!amdahl!JUTS!cd.amdahl.com!jjs40
- From: jjs40@cd.amdahl.com (John Sullivan)
- Newsgroups: comp.arch
- Subject: Re: Super-pipelining
- Message-ID: <4aG902Af30kD01@JUTS.ccc.amdahl.com>
- Date: 30 Dec 92 23:04:48 GMT
- References: <1992Dec30.175717.15249@dcc.uchile.cl>
- Sender: netnews@ccc.amdahl.com
- Organization: Amdahl Corporation, Sunnyvale CA
- Lines: 27
-
- In article <1992Dec30.175717.15249@dcc.uchile.cl>, pchris@dcc.uchile.cl
- (Chris Perleberg) writes:
- >After reading the Data Sheet of the 21064, I find nothing that seems
- >to
- >indicate the 21064 is super-pipelined, at least in terms of the common
- >definition of super-pipelined. Is DEC redefining the word
- >"super-pipeline"?
- >Anybody out there that can explain?
-
- Although it's not obvious, this term really applies more to the cache
- structure of a CPU pipeline than anything else. (If you don't believe me,
- flame away.) Here's the definition that I suggest:
-
- Super-pipelined:
- The primary caches in the CPU pipeline are partitioned across two or
- more pipeline stages. Because cache access time is often a cycle-time
- determining path, the designers have decided to split the time across
- more than one cycle. The tradeoff is a faster instruction issue rate
- due to a shorter cycle time) versus longer load-execute and
- conditional-branch interlocks (leading to a higher CPI.)
-
- The term "super-pipelined" has been widely used (and abused) since the
- late 80's. Super-pipelined machines have existed for about 20 years.
-
- --
- John Sullivan, Engineer/Computer Development. Email: jjs40@cd.amdahl.com
- Amdahl Corporation, Sunnyvale CA. Phone: (408)746-4688
-