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- From: tim@Apple.COM (Tim Olson)
- Newsgroups: comp.arch
- Subject: Re: Alpha and Super-pipelining
- Message-ID: <76004@apple.apple.COM>
- Date: 31 Dec 92 00:01:14 GMT
- References: <1992Dec30.175717.15249@dcc.uchile.cl>
- Organization: Apple Computer Inc, Cupertino, CA
- Lines: 18
-
- In article <1992Dec30.175717.15249@dcc.uchile.cl> pchris@dcc.uchile.cl writes:
-
- |After reading the material available about the Alpha, I noticed that it was
- |mentioned a few times that the first implementation of the Alpha, the 21064,
- |is *super-pipelined* as well as superscalar.
- |
- |After reading the Data Sheet of the 21064, I find nothing that seems to
- |indicate the 21064 is super-pipelined, at least in terms of the common
- |definition of super-pipelined. Is DEC redefining the word "super-pipeline"?
- |Anybody out there that can explain?
-
- I believe some "simple" ALU instructions, such as shift, issue at a
- single-cycle rate, but have a 2-cycle latency.
-
- --
- -- Tim Olson
- Apple Computer Inc. / Somerset
- (tim@apple.com)
-