NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/sci/math/research/611

Text File | 1992-12-21 | 5.3 KB | 128 lines

Newsgroups: sci.math.research
Path: sparky!uunet!zaphod.mps.ohio-state.edu!moe.ksu.ksu.edu!ux1.cso.uiuc.edu!news.cso.uiuc.edu!dan
From: [e-mail] (T. Kostelijk 43897)
Subject: Postdoc vacancy for multi-rate / protocol IC-design verification
Message-ID: <[e-mail]>
Originator: [e-mail]
Sender: Daniel Grayson <[e-mail]>
X-Submissions-To: [e-mail]
Old-Return-Path: <[e-mail]>
Organization: none
X-Administrivia-To: [e-mail]
Approved: Daniel Grayson <[e-mail]>
Date: Fri, 18 Dec 1992 15:29:34 GMT
Lines: 112

Subject: Postdoc vacancy for multi-rate / protocol verification
         in IC-design, second round.

Several months ago, a postdoc vacancy has been created by a
proposal of the Philips Research Lab Eindhoven (The Netherlands),
that has been accepted by the European Communities program
"Human Capital and Mobility".

The technical part of the proposal is appended to this announcement.

We search for skilled candidates, who have received a PhD or are
about to receive a PhD in computer science, mathematics or electronic
engineering and who are inhabitants of a non-Dutch EC country.

In this second round, we expect candidates to apply within 2 months.
The application letters will be dealt with in the order they come in.
The 18-month postdoc period must start between Januari 1st
and June 1st, 1993. The conditions of employment,
which are quite favourable, are determined by the EC.

An application can be send in by (e)mailing an application letter,
containing your CV, motivation to apply, qualification, etc., to
the address below. When sending email, latex source is fine.

A.P. Kostelijk,
Philips Research Lab Eindhoven,
P.O. Box 80000, WAY 4.47,
5600 JA Eindhoven
The Netherlands
Phone: [phone]
Fax:   [phone]
Email: [e-mail]



TITLE

Formal verification of multi-rate IC-designs.

DETAILED DESCRIPTION OF THE PROJECT

The aim of the project is to solve fundamental problems that
prevent the verification of multi-rate IC-designs.
A multi-rate IC is a digital Integrated Circuit of which
different parts run on different clock frequencies,
and for which no simple timing relation
between the constituent parts exist.
Proving correctness of the communication between these parts
is difficult. From a functional point of view,
the communication can be multi-synchronous or even asynchronous.
A digital signal processor for example, can consist of
different parts running with different sampling frequencies,
again with different clock frequencies, and the communication
can be multi-synchronous, or ``asynchronous" via
synchronised interrupts.

Until now, formal verification methods for IC design focus
on single clock systems only. Recent advances in this area,
such as for Finite State Machine verification and Retiming
verification are a step forward in verifying single clock parts,
but they do not address multi-rate IC-designs.
There is no known method to verify non-trivial multi-rate designs
in a reasonable way.
The verification method currently applied, based on simulation,
is insufficient to get a reasonable impression of the correctness
of the communication between the constituent parts.
Only a very limited set of interrupts  and input patterns
can be simulated because of the long simulation times that are needed.
Checking synchronisation and setup procedures for every possible
situation is therefore prohibitive.
The only reasonable ``verification method" remaining is to test
how the actual IC behaves after it has been processed.

The research project will focus on the fundamental question of
how the communication can be modeled, and how the implementation
can be proven correct, while assuming that the constituent
(single clock) parts of the IC design are correct.

The strategy for tackling the verification problem in
multi-rate IC designs will be based on exploiting the knowledge
of formal verification methods in strong combination with
IC design expertise and know-how. In this way, it is expected
that parts of the verification problem will be solved,
in particular those items that are most relevant for the IC designers.


RELEVANCE OF THE PROJECT TO THE TRAINING OF YOUNG RESEARCHERS

The Philips Research IC Design Centre offers the researcher
an ideal environment to attack this challenging problem.
It has an outstanding reputation for
IC design research and CAD for VLSI in general,
and for IC design verification in particular.
It combines both the academic freedom to explore new ideas
and the challenge to apply the ideas on industrial designs.
In this sense we have shown several times that
the combination of our CAD research
and IC design expertise leads to unique CAD products
that are very useful in industrial design environments.


INDUSTRIAL, ECONOMIC AND SOCIAL RELEVANCE OF THE RESEARCH

Continuous advances in IC technology
allow the integration of functions of ever growing complexity.
The number of single chip multi-rate system designs is growing rapidly,
but its verification is at present already a major bottleneck.
Therefore, multi-rate verification has become extremely important
to guarantee first time right IC designs, and the relevance
grows even more with time. First time right IC designs are essential
to reduce the time to market of new electronic products.