NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/sys/amiga/hardware/19888

Internet Message Format | 1992-11-18 | 1.6 KB

Path: sparky!uunet!mcsun!news.funet.fi!news.cs.tut.fi!mk59200
From: [e-mail] (Kolkka Markku Olavi)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Parity
Date: 18 Nov 1992 16:13:10 GMT
Organization: Tampere University of Technology
Lines: 23
Distribution: world
Message-ID: <[e-mail]>
References: <[e-mail]> <[e-mail]> <[e-mail]>
NNTP-Posting-Host: ketturastas.cs.tut.fi

In article <[e-mail]> [e-mail] writes:
>>>EDC (Error Detection and Correction) is also known as ECC (why, I don't
>>>know).  On Unibus VAXen, ECC memory is 10 bits/byte; it can *correct*
>>>single bit errors and detect double bit errors.
>
>"The ECC scheme used in the memory subsystem is capable of detecting a single
>or double bit error.  It is also capable of correcting all single bit errors.
>This is accomplished by storing eight check bits, along with the 64 data bits
>in each memory location (i.e. quadword access to memory).

So, the ECC system _doesn't_ use 10 (or 9) bits per byte, it uses 72 bits per
quadword.  There is a big difference, even if the total amount of bits is
similar. With this ECC scheme you cant read or write individual bytes,
because changing a single byte will affect several checkbits and the new
values of the checkbits depend on other data in the block.

Of course all this is hidden from the CPU and software by the memory
controller, but it complicates and slows down the memory/CPU interface.

--
    Markku Kolkka
    [e-mail]