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  1. Path: sparky!uunet!wupost!usc!sdd.hp.com!uakari.primate.wisc.edu!usenet.coe.montana.edu!news.u.washington.edu!hardy.u.washington.edu!echen
  2. From: echen@hardy.u.washington.edu (Ed Chen)
  3. Newsgroups: comp.lang.verilog
  4. Subject: Re: Verilog Synthesis
  5. Message-ID: <1992Jul29.081334.29463@u.washington.edu>
  6. Date: 29 Jul 92 08:13:34 GMT
  7. References: <1992Jul29.030523.28537@leland.Stanford.EDU>
  8. Sender: news@u.washington.edu (USENET News System)
  9. Organization: University of Washington, Seattle
  10. Lines: 9
  11.  
  12. In article <1992Jul29.030523.28537@leland.Stanford.EDU> vasu@leland.Stanford.EDU (Swaminatha Vasudevan) writes:
  13. >Who makes ASIC synthesis s/w for Verilog besides Synopsys and Cadence?
  14. >
  15. >\V
  16.  
  17. COMPASS Design Automation Tools - VLSI Technologies, Phoenix AZ.
  18.  
  19.                     Ed
  20.                     echen@u.washington.edu
  21.