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Z801ISET.TBL
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1993-05-21
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table 4 0
Z80/Z180 Instruction Set
HEX OPCODE MNEMONIC OPERANDS OPERATION
_
8E ADC A,(HL) Add with carry A, indirect (HL)
DD 8E ii ADC A,(IX+ii) Add with carry A, indexed (IX+ii)
FD 8E ii ADC A,(IY+ii) Add with carry A, indexed (IY+ii)
_
8F ADC A,A Add with carry A, register
88 ADC A,B
89 ADC A,C
8A ADC A,D
8B ADC A,E
8C ADC A,H
8D ADC A,L
_
CE nn ADC A,nn Add with carry A, immediate
_
ED 4A ADC HL,BC Add with carry HL, register
ED 5A ADC HL,DE
ED 6A ADC HL,HL
ED 7A ADC HL,SP
_
86 ADD A,(HL) Add A, indirect (HL)
DD 86 ii ADD A,(IX+ii) Add A, indexed (IX+ii)
FD 86 ii ADD A,(IY+ii) Add A, indexed (IY+ii)
_
87 ADD A,A Add A with register
80 ADD A,B
81 ADD A,C
82 ADD A,D
83 ADD A,E
84 ADD A,H
85 ADD A,L
_
C6 nn ADD A,nn Add A, immediate
_
09 ADD HL,BC Add HL with register
19 ADD HL,DE
29 ADD HL,HL
39 ADD HL,SP
_
DD 09 ADD IX,BC Add IX with register
DD 19 ADD IX,DE
DD 29 ADD IX,IX
DD 39 ADD IX,SP
_
FD 09 ADD IY,BC Add IX with register
FD 19 ADD IY,DE
FD 29 ADD IY,IY
FD 39 ADD IY,SP
_
A6 AND (HL) Logical AND A, indirect (HL)
DD A6 ii AND (IX+ii) Logical AND A, indexed (IX+ii)
FD A6 ii AND (IY+ii) Logical AND A, indexed (IY+ii)
_
A7 AND A Logical AND A with register
A0 AND B
A1 AND C
A2 AND D
A3 AND E
A4 AND H
A5 AND L
_
E6 nn AND nn Logical AND A, immediate
_
CB 46 BIT 0,(HL) Test bit 0, indirect (HL)
DD CB ii 46 BIT 0,(IX+ii) Test bit 0, indexed (IX+ii)
FD CB ii 46 BIT 0,(IY+ii) Test bit 0, indexed (IY+ii)
_
CB 47 BIT 0,A Test bit 0 of register
CB 40 BIT 0,B
CB 41 BIT 0,C
CB 42 BIT 0,D
CB 43 BIT 0,E
CB 44 BIT 0,H
CB 45 BIT 0,L
_
CB 4E BIT 1,(HL) Test bit 1, indirect (HL)
DD CB ii 4E BIT 1,(IX+ii) Test bit 1, indexed (IX+ii)
FD CB ii 4E BIT 1,(IY+ii) Test bit 1, indexed (IY+ii)
_
CB 4F BIT 1,A Test bit 1 of register
CB 48 BIT 1,B
CB 49 BIT 1,C
CB 4A BIT 1,D
CB 4B BIT 1,E
CB 4C BIT 1,H
CB 4D BIT 1,L
_
CB 56 BIT 2,(HL) Test bit 2, indirect (HL)
DD CB ii 56 BIT 2,(IX+ii) Test bit 2, indexed (IX+ii)
FD CB ii 56 BIT 2,(IY+ii) Test bit 2, indexed (IY+ii)
_
CB 57 BIT 2,A Test bit 2 of register
CB 50 BIT 2,B
CB 51 BIT 2,C
CB 52 BIT 2,D
CB 53 BIT 2,E
CB 54 BIT 2,H
CB 55 BIT 2,L
_
CB 5E BIT 3,(HL) Test bit 3, indirect (HL)
DD CB ii 5E BIT 3,(IX+ii) Test bit 3, indexed (IX+ii)
FD CB ii 5E BIT 3,(IY+ii) Test bit 3, indexed (IY+ii)
_
CB 5F BIT 3,A Test bit 3 of register
CB 58 BIT 3,B
CB 59 BIT 3,C
CB 5A BIT 3,D
CB 5B BIT 3,E
CB 5C BIT 3,H
CB 5D BIT 3,L
_
CB 66 BIT 4,(HL) Test bit 4, indirect (HL)
DD CB ii 66 BIT 4,(IX+ii) Test bit 4, indexed (IX+ii)
FD CB ii 66 BIT 4,(IY+ii) Test bit 4, indexed (IY+ii)
_
CB 67 BIT 4,A Test bit 4 of register
CB 60 BIT 4,B
CB 61 BIT 4,C
CB 62 BIT 4,D
CB 63 BIT 4,E
CB 64 BIT 4,H
CB 65 BIT 4,L
_
CB 6E BIT 5,(HL) Test bit 5, indirect (HL)
DD CB ii 6E BIT 5,(IX+ii) Test bit 5, indexed (IX+ii)
FD CB ii 6E BIT 5,(IY+ii) Test bit 5, indexed (IY+ii)
_
CB 6F BIT 5,A Test bit 5 of register
CB 68 BIT 5,B
CB 69 BIT 5,C
CB 6A BIT 5,D
CB 6B BIT 5,E
CB 6C BIT 5,H
CB 6D BIT 5,L
_
CB 76 BIT 6,(HL) Test bit 6, indirect (HL)
DD CB ii 76 BIT 6,(IX+ii) Test bit 6, indexed (IX+ii)
FD CB ii 76 BIT 6,(IY+ii) Test bit 7, indexed (IY+ii)
_
CB 77 BIT 6,A Test bit 6 of register
CB 70 BIT 6,B
CB 71 BIT 6,C
CB 72 BIT 6,D
CB 73 BIT 6,E
CB 74 BIT 6,H
CB 75 BIT 6,L
_
CB 7E BIT 7,(HL) Test bit 7, indirect (HL)
DD CB ii 7E BIT 7,(IX+ii) Test bit 7, indexed (IX+ii)
FD CB ii 7E BIT 7,(IY+ii) Test bit 7, indexed (IY+ii)
_
CB 7F BIT 7,A Test bit 7 of register
CB 78 BIT 7,B
CB 79 BIT 7,C
CB 7A BIT 7,D
CB 7B BIT 7,E
CB 7C BIT 7,H
CB 7D BIT 7,L
_
CD ll hh CALL hhll Call subroutine
_
DC ll hh CALL C,hhll Call if C set
FC ll hh CALL M,hhll Call if minus
D4 ll hh CALL NC,hhll Call if C clear
C4 ll hh CALL NZ,hhll Call if not zero
F4 ll hh CALL P,hhll Call if plus
EC ll hh CALL PE,hhll Call if parity even
E4 ll hh CALL PO,hhll Call if parity oii
CC ll hh CALL Z,hhll Call if zero
_
3F CCF Complement carry flag
_
BE CP (HL) Compare A, indirect (HL)
DD BE ii CP (IX+ii) Compare A, indexed (IX+ii)
FD BE ii CP (IY+ii) Compare A, indexed (IY+ii)
_
BF CP A Compare A with register
B8 CP B
B9 CP C
BA CP D
BB CP E
BC CP H
BD CP L
_
FE nn CP nn Compare A, immediate
_
ED A9 CPD Compare with decrement
Compare A register with
memory (HL), decrement HL
and BC. Z flag reflects
comparison, P/V flag is
cleared if BC is 0
_
ED B9 CPDR Block compare with decrement
Compare A register with (HL),
decrement HL and BC, if BC
is not zero and A did not match
(HL) then repeat. On termination
Z is set if match was found,
P/V is clear if BC is zero.
_
ED A1 CPI Compare with increment
Compare A register with
memory (HL), increment HL,
decrement BC. Z flag is
set to reflect comparison,
P/V flag is clear if BC is 0
_
ED B1 CPIR Block Compare with increment
Compare A register with (HL),
increment HL, decrement BC, if
BC is not 0 and A did not match
(HL) then repeat. On termination
Z is set if match was found,
P/V is clear if BC is zero.
_
2F CPL 1's Complement A
_
27 DAA Decimal Adjust A
_
35 DEC (HL) Decrement, indirect (HL)
DD 35 ii DEC (IX+ii) Decrement, indexed (IX+ii)
FD 35 ii DEC (IY+ii) Decrement, indexed (IY+ii)
_
3D DEC A Decrement 8 bit register
05 DEC B
0D DEC C
15 DEC D
1D DEC E
25 DEC H
2D DEC L
_
0B DEC BC Decrement 16 bit register
1B DEC DE
2B DEC HL
DD 2B DEC IX
FD 2B DEC IY
3B DEC SP
_
F3 DI Disable interrupts
_
10 rr DJNZ rr Decrement B and jump if not 0
_
FB EI Enable interrupts
_
E3 EX (SP),HL Exchange HL with top of stack
DD E3 EX (SP),IX Exchange IX with top of stack
FD E3 EX (SP),IY Exchange IY with top of stack
08 EX AF,AF' Exchange AF with AF'
EB EX DE,HL Exchange DE with HL
_
D9 EXX Exchange BC,DE,HL, BC',DE',HL'
_
76 HALT Suspend execution
_
ED 46 IM 0 Set interrupt mode 0
ED 56 IM 1 Set interrupt mode 1
ED 5E IM 2 Set interrupt mode 2
_
DB pp IN A,(pp) Load A from port (pp)
Output pp on low half of
address bus and A register
on high half of address bus.
_
ED 78 IN A,(C) Load register from port (BC)
ED 40 IN B,(C) Output C register on low
ED 48 IN C,(C) half of address bus and B
ED 50 IN D,(C) register on high half of
ED 58 IN E,(C) address bus. Use this on
ED 60 IN H,(C) processors with 16 bit I/O
ED 68 IN L,(C) address decoding.
_
ED 38 pp IN0 A,(pp) Z180: Load register from
ED 00 pp IN0 B,(pp) port (00pp). Output pp on
ED 08 pp IN0 C,(pp) low half of address bus and
ED 10 pp IN0 D,(pp) 00H on high half of address
ED 18 pp IN0 E,(pp) bus. Use this instruction
ED 20 pp IN0 H,(pp) instead of IN A,(pp) on the
ED 28 pp IN0 L,(pp) Z180 and 64180 processors.
_
34 INC (HL) Increment, indirect (HL)
DD 34 ii INC (IX+ii) Increment, indexed (IX+ii)
FD 34 ii INC (IY+ii) Increment, indexed (IY+ii)
_
3C INC A Increment 8 bit register
04 INC B
0C INC C
14 INC D
1C INC E
24 INC H
2C INC L
_
03 INC BC Increment 16 bit register
13 INC DE
23 INC HL
DD 23 INC IX
FD 23 INC IY
33 INC SP
_
ED AA IND Input with decrement.
Input port (BC) and write
result to address (HL).
Decrement B and HL registers.
Set Z flag if B is zero.
_
ED BA INDR Block input with decrement.
Input port (BC) and write
result to address (HL).
Decrement B and HL registers,
repeat if B is not zero.
_
ED A2 INI Input with increment.
Input port (BC) and write
result to address (HL).
Decrement B, increment HL.
Set Z flag if B is zero.
_
ED B2 INIR Block input with increment.
Input port (BC) and write
result to address (HL).
Decrement B, increment HL,
repeat if B is not zero.
_
C3 ll hh JP hhll Jump
E9 JP (HL) Jump to HL
DD E9 JP (IX) Jump to IX
FD E9 JP (IY) Jump to IY
_
DA ll hh JP C,hhll Jump if carry set
FA ll hh JP M,hhll Jump if minus
D2 ll hh JP NC,hhll Jump if carry clear
C2 ll hh JP NZ,hhll Jump if not zero
F2 ll hh JP P,hhll Jump if plus
EA ll hh JP PE,hhll Jump if parity even
E2 ll hh JP PO,hhll Jump if parity oii
CA ll hh JP Z,hhll Jump if zero
_
18 rr JR rr Jump relative
_
38 rr JR C,rr Jump relative if carry set
30 rr JR NC,rr Jump relative if carry clear
20 rr JR NZ,rr Jump relative if not zero
28 rr JR Z,rr Jump relative if zero
_
02 LD (BC),A Store A indirect (BC)
12 LD (DE),A Store A indirect (DE)
_
77 LD (HL),A Store register indirect (HL)
70 LD (HL),B
71 LD (HL),C
72 LD (HL),D
73 LD (HL),E
74 LD (HL),H
75 LD (HL),L
_
36 nn LD (HL),nn Store immediate indirect (HL)
_
DD 77 ii LD (IX+ii),A Store register indexed (IX+ii)
DD 70 ii LD (IX+ii),B
DD 71 ii LD (IX+ii),C
DD 72 ii LD (IX+ii),D
DD 73 ii LD (IX+ii),E
DD 74 ii LD (IX+ii),H
DD 75 ii LD (IX+ii),L
_
DD 36 ii nn LD (IX+ii),nn Store immediate indexed (IX+ii)
_
FD 77 ii LD (IY+ii),A Store register indexed (IY+ii)
FD 70 ii LD (IY+ii),B
FD 71 ii LD (IY+ii),C
FD 72 ii LD (IY+ii),D
FD 73 ii LD (IY+ii),E
FD 74 ii LD (IY+ii),H
FD 75 ii LD (IY+ii),L
_
FD 36 ii nn LD (IY+ii),nn Store immediate indexed (IY+ii)
_
32 ll hh LD (hhll),A Store A to memory
_
ED 43 ll hh LD (hhll),BC Store BC to memory
ED 53 ll hh LD (hhll),DE Store DE to memory
22 ll hh LD (hhll),HL Store HL to memory
DD 22 ll hh LD (hhll),IX Store IX to memory
FD 22 ll hh LD (hhll),IY Store IY to memory
ED 73 ll hh LD (hhll),SP Store SP to memory
_
3A ll hh LD A,(hhll) Load A from memory
_
0A LD A,(BC) Load A, indirect (BC)
1A LD A,(DE) Load A, indirect (DE)
_
7E LD A,(HL) Load A, indirect (HL)
DD 7E ii LD A,(IX+ii) Load A, indexed (IX+ii)
FD 7E ii LD A,(IY+ii) Load A, indexed (IY+ii)
_
7F LD A,A Load A from register
78 LD A,B
79 LD A,C
7A LD A,D
7B LD A,E
7C LD A,H
7D LD A,L
_
ED 57 LD A,I Load A from I register
ED 5F LD A,R Load A from R register
_
3E nn LD A,nn Load A, immediate
_
46 LD B,(HL) Load B, indirect (HL)
DD 46 ii LD B,(IX+ii) Load B, indexed (IX+ii)
FD 46 ii LD B,(IY+ii) Load B, indexed (IY+ii)
_
47 LD B,A Load B from register
40 LD B,B
41 LD B,C
42 LD B,D
43 LD B,E
44 LD B,H
45 LD B,L
_
06 nn LD B,nn Load B, immediate
_
ED 4B ll hh LD BC,(hhll) Load BC from memory
01 ll hh LD BC,hhll Load BC, immediate
_
4E LD C,(HL) Load C, indirect (HL)
DD 4E ii LD C,(IX+ii) Load C, indexed (IX+ii)
FD 4E ii LD C,(IY+ii) Load C, indexed (IY+ii)
_
4F LD C,A Load C from register
48 LD C,B
49 LD C,C
4A LD C,D
4B LD C,E
4C LD C,H
4D LD C,L
_
0E nn LD C,nn Load C, immediate
_
56 LD D,(HL) Load D, indirect (HL)
DD 56 ii LD D,(IX+ii) Load D, indexed (IX+ii)
FD 56 ii LD D,(IY+ii) Load D, indexed (IY+ii)
_
57 LD D,A Load D from register
50 LD D,B
51 LD D,C
52 LD D,D
53 LD D,E
54 LD D,H
55 LD D,L
_
16 nn LD D,nn Load D, immediate
_
ED 5B ll hh LD DE,(hhll) Load DE from memory
11 ll hh LD DE,hhll Load DE, immediate
_
5E LD E,(HL) Load E, indirect (HL)
DD 5E ii LD E,(IX+ii) Load E, indexed (IX+ii)
FD 5E ii LD E,(IY+ii) Load E, indexed (IY+ii)
_
5F LD E,A Load E from register
58 LD E,B
59 LD E,C
5A LD E,D
5B LD E,E
5C LD E,H
5D LD E,L
_
1E nn LD E,nn Load E, immediate
_
66 LD H,(HL) Load H, indirect (HL)
DD 66 ii LD H,(IX+ii) Load H, indexed (IX+ii)
FD 66 ii LD H,(IY+ii) Load H, indexed (IY+ii)
_
67 LD H,A Load H from register
60 LD H,B
61 LD H,C
62 LD H,D
63 LD H,E
64 LD H,H
65 LD H,L
_
26 nn LD H,nn Load H, immediate
_
2A ll hh LD HL,(hhll) Load HL from memory
21 ll hh LD HL,hhll Load HL, immediate
_
ED 47 LD I,A Load register I from A
_
DD 2A ll hh LD IX,(hhll) Load IX from memory
DD 21 ll hh LD IX,hhll Load IX, immediate
_
FD 2A ll hh LD IY,(hhll) Load IY from memory
FD 21 ll hh LD IY,hhll Load IY, immediate
_
6E LD L,(HL) Load L, indirect (HL)
DD 6E ii LD L,(IX+ii) Load L, indexed (IX+ii)
FD 6E ii LD L,(IY+ii) Load L, indexed (IY+ii)
_
6F LD L,A Load L from register
68 LD L,B
69 LD L,C
6A LD L,D
6B LD L,E
6C LD L,H
6D LD L,L
_
2E nn LD L,nn Load L, immediate
_
ED 4F LD R,A Load R register from A
_
ED 7B ll hh LD SP,(hhll) Load SP from memory
F9 LD SP,HL Load SP from HL
DD F9 LD SP,IX Load SP from IX
FD F9 LD SP,IY Load SP from IY
31 ll hh LD SP,hhll Load SP from memory
_
ED A8 LDD Load with decrement.
Copy memory (HL) to (DE),
decrement HL, DE and BC,
clear P/V flag if BC is 0
_
ED B8 LDDR Block load with decrement.
Copy memory (HL) to (DE),
decrement HL, DE and BC,
repeat if BC is not 0
_
ED A0 LDI Load with increment.
Copy memory (HL) to (DE)
inc HL and DE, dec BC,
clear P/V flag if BC is 0
_
ED B0 LDIR Block load with increment
Copy memory (HL) to (DE),
inc HL and DE, dec BC,
repeat if BC is not 0
_
ED 4C MLT BC Z180: multiply BC = B x C
ED 5C MLT DE Z180: multiply DE = D x E
ED 6C MLT HL Z180: multiply HL = H x L
ED 7C MLT SP Z180: multiply SP = SPH x SPL
_
ED 44 NEG 2's complement negate A
_
00 NOP No operation
_
B6 OR (HL) Logical OR A, indirect (HL)
DD B6 ii OR (IX+ii) Logical OR A, indexed (IX+ii)
FD B6 ii OR (IY+ii) Logical OR A, indexed (IY+ii)
_
B7 OR A Logical OR A with register
B0 OR B
B1 OR C
B2 OR D
B3 OR E
B4 OR H
B5 OR L
_
F6 nn OR nn Logical OR A, immediate
_
ED BB OTDR Block output with decrement.
Output memory (HL) to port
(BC), decrement HL and B,
repeat if B is not 0
_
ED 9B OTDMR Z180: Block output with
Decrement. Like OTDR but
outputs 00H on high half
of address bus. Use in
place of OTDR on the Z180
and 64180 processors.
_
ED B3 OTIR Block output with increment.
Output memory (HL) to port
(BC), increment HL, decrement
B, repeat if B is not 0
_
ED 93 OTIMR Z180: Block output with
Increment. Like OTIR but
outputs 00H on high half
of address bus. Use in
place of OTIR on the Z180
and 64180 processors.
_
D3 pp OUT (pp),A Output A to port (pp).
Output pp on low half of
address bus, A register on
high half of address bus and
on data bus.
_
ED 79 OUT (C),A Output register to port (BC)
ED 41 OUT (C),B Output C register on low half
ED 49 OUT (C),C of address bus, B register on
ED 51 OUT (C),D high half of address bus. Use
ED 59 OUT (C),E this instruction instead of
ED 61 OUT (C),H OUT (pp),A on processors with
ED 69 OUT (C),L 16 bit I/O decoding.
_
ED 39 pp OUT0 (pp),A Z180: Output register to port
ED 01 pp OUT0 (pp),B (00pp), output 00H on high byte
ED 09 pp OUT0 (pp),C of address bus. Use this instead
ED 11 pp OUT0 (pp),D of OUT (pp),A on the Z180 and
ED 19 pp OUT0 (pp),E 64180 processors.
ED 21 pp OUT0 (pp),H
ED 29 pp OUT0 (pp),L
_
ED AB OUTD Output with decrement.
Output memory (HL) to port
(BC), decrement HL and B,
set Z flag if B is 0.
_
ED 8B OTDM Z180: Output with decrement.
Like OUTD but outputs 00H
on high half of address bus,
use instead of OUTD on the
Z180 and 64180 processors.
_
ED A3 OUTI Output with increment.
Output memory (HL) to port
(BC), increment HL, decrement
B, set Z flag if B is 0
_
ED 83 OTIM Z180: Output with increment.
Like OUTI but outputs 00H
on high half of address bus,
use instead of OUTI on the
Z180 and 64180 processors.
_
F1 POP AF Pop AF from stack
C1 POP BC Pop BC from stack
D1 POP DE Pop DE from stack
E1 POP HL Pop HL from stack
DD E1 POP IX Pop IX from stack
FD E1 POP IY Pop IY from stack
_
F5 PUSH AF Push AF on stack
C5 PUSH BC Push BC on stack
D5 PUSH DE Push DE on stack
E5 PUSH HL Push HL on stack
DD E5 PUSH IX Push IX on stack
FD E5 PUSH IY Push IY on stack
_
CB 86 RES 0,(HL) Clear bit 0, indirect (HL)
DD CB ii 86 RES 0,(IX+ii) Clear bit 0, indexed (IX+ii)
FD CB ii 86 RES 0,(IY+ii) Clear bit 0, indexed (IY+ii)
_
CB 87 RES 0,A Clear bit 0 of register
CB 80 RES 0,B
CB 81 RES 0,C
CB 82 RES 0,D
CB 83 RES 0,E
CB 84 RES 0,H
CB 85 RES 0,L
_
CB 8E RES 1,(HL) Clear bit 1, indirect (HL)
DD CB ii 8E RES 1,(IX+ii) Clear bit 1, indexed (IX+ii)
FD CB ii 8E RES 1,(IY+ii) Clear bit 1, indexed (IY+ii)
_
CB 8F RES 1,A Clear bit 1 of register
CB 88 RES 1,B
CB 89 RES 1,C
CB 8A RES 1,D
CB 8B RES 1,E
CB 8C RES 1,H
CB 8D RES 1,L
_
CB 96 RES 2,(HL) Clear bit 2, indirect (HL)
DD CB ii 96 RES 2,(IX+ii) Clear bit 2, indexed (IX+ii)
FD CB ii 96 RES 2,(IY+ii) Clear bit 2, indexed (IY+ii)
_
CB 97 RES 2,A Clear bit 2 of register
CB 90 RES 2,B
CB 91 RES 2,C
CB 92 RES 2,D
CB 93 RES 2,E
CB 94 RES 2,H
CB 95 RES 2,L
_
CB 9E RES 3,(HL) Clear bit 3, indirect (HL)
DD CB ii 9E RES 3,(IX+ii) Clear bit 3, indexed (IX+ii)
FD CB ii 9E RES 3,(IY+ii) Clear bit 3, indexed (IY+ii)
_
CB 9F RES 3,A Clear bit 3 of register
CB 98 RES 3,B
CB 99 RES 3,C
CB 9A RES 3,D
CB 9B RES 3,E
CB 9C RES 3,H
CB 9D RES 3,L
_
CB A6 RES 4,(HL) Clear bit 4, indirect (HL)
DD CB ii A6 RES 4,(IX+ii) Clear bit 4, indexed (IX+ii)
FD CB ii A6 RES 4,(IY+ii) Clear bit 4, indexed (IY+ii)
_
CB A7 RES 4,A Clear bit 4 of register
CB A0 RES 4,B
CB A1 RES 4,C
CB A2 RES 4,D
CB A3 RES 4,E
CB A4 RES 4,H
CB A5 RES 4,L
_
CB AE RES 5,(HL) Clear bit 5, indirect (HL)
DD CB ii AE RES 5,(IX+ii) Clear bit 5, indexed (IX+ii)
FD CB ii AE RES 5,(IY+ii) Clear bit 5, indexed (IY+ii)
_
CB AF RES 5,A Clear bit 5 of register
CB A8 RES 5,B
CB A9 RES 5,C
CB AA RES 5,D
CB AB RES 5,E
CB AC RES 5,H
CB AD RES 5,L
_
CB B6 RES 6,(HL) Clear bit 6, indirect (HL)
DD CB ii B6 RES 6,(IX+ii) Clear bit 6, indexed (IX+ii)
FD CB ii B6 RES 6,(IY+ii) Clear bit 6, indexed (IY+ii)
_
CB B7 RES 6,A Clear bit 6 of register
CB B0 RES 6,B
CB B1 RES 6,C
CB B2 RES 6,D
CB B3 RES 6,E
CB B4 RES 6,H
CB B5 RES 6,L
_
CB BE RES 7,(HL) Clear bit 7, indirect (HL)
DD CB ii BE RES 7,(IX+ii) Clear bit 7, indexed (IX+ii)
FD CB ii BE RES 7,(IY+ii) Clear bit 7, indexed (IY+ii)
_
CB BF RES 7,A Clear bit 7 of register
CB B8 RES 7,B
CB B9 RES 7,C
CB BA RES 7,D
CB BB RES 7,E
CB BC RES 7,H
CB BD RES 7,L
_
C9 RET Return from subroutine
_
D8 RET C Return if carry set
F8 RET M Return if minus
D0 RET NC Return if carry clear
C0 RET NZ Return if zero
F0 RET P Return if plus
E8 RET PE Return if parity even
E0 RET PO Return if parity oii
C8 RET Z Return if zero
_
ED 4D RETI Return from interrupt
ED 45 RETN Return from NMI
_
CB 16 RL (HL) 9 bit rotate left, indirect (HL)
DD CB ii 16 RL (IX+ii) 9 bit rotate left, indexed (IX+ii)
FD CB ii 16 RL (IY+ii) 9 bit rotate left, indexed (IY+ii)
_
CB 17 RL A 9 bit rotate left register
CB 10 RL B
CB 11 RL C
CB 12 RL D
CB 13 RL E
CB 14 RL H
CB 15 RL L
_
17 RLA 9 bit rotate left A
_
CB 06 RLC (HL) 8 bit rotate left, indirect (HL)
DD CB ii 06 RLC (IX+ii) 8 bit rotate left, indexed (IX+ii)
FD CB ii 06 RLC (IY+ii) 8 bit rotate left, indexed (IY+ii)
_
CB 07 RLC A 8 bit rotate left register
CB 00 RLC B
CB 01 RLC C
CB 02 RLC D
CB 03 RLC E
CB 04 RLC H
CB 05 RLC L
_
07 RLCA 8 bit rotate right A
_
ED 6F RLD Rotate left decimal
_
CB 1E RR (HL) 9 bit rotate right, indirect (HL)
DD CB ii 1E RR (IX+ii) 9 bit rotate right, indexed (IX+ii)
FD CB ii 1E RR (IY+ii) 9 bit rotate right, indexed (IY+ii)
_
CB 1F RR A 9 bit rotate right register
CB 18 RR B
CB 19 RR C
CB 1A RR D
CB 1B RR E
CB 1C RR H
CB 1D RR L
_
1F RRA 9 bit rotate right A
_
CB 0E RRC (HL) 8 bit rotate right, indirect (HL)
DD CB ii 0E RRC (IX+ii) 8 bit rotate right, indexed (IX+ii)
FD CB ii 0E RRC (IY+ii) 8 bit rotate right, indexed (IY+ii)
_
CB 0F RRC A 8 bit rotate right register
CB 08 RRC B
CB 09 RRC C
CB 0A RRC D
CB 0B RRC E
CB 0C RRC H
CB 0D RRC L
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0F RRCA 8 bit rotate right A
_
ED 67 RRD Rotate right decimal
_
C7 RST 00H CALL 0000H
CF RST 08H CALL 0008H
D7 RST 10H CALL 0010H
DF RST 18H CALL 0018H
E7 RST 20H CALL 0020H
EF RST 28H CALL 0028H
F7 RST 30H CALL 0030H
FF RST 38H CALL 0038H
_
9E SBC A,(HL) SUB with borrow A, indirect (HL)
DD 9E ii SBC A,(IX+ii) SUB with borrow A, indexed (IX+ii)
FD 9E ii SBC A,(IY+ii) SUB with borrow A, indexed (IY+ii)
_
9F SBC A,A Subtract with borrow A, register
98 SBC A,B
99 SBC A,C
9A SBC A,D
9B SBC A,E
9C SBC A,H
9D SBC A,L
_
DE nn SBC A,nn SUB with borrow A, immediate
_
ED 42 SBC HL,BC SUB with borrow HL, register
ED 52 SBC HL,DE
ED 62 SBC HL,HL
ED 72 SBC HL,SP
_
37 SCF Set carry flag
_
CB C6 SET 0,(HL) Set bit 0, indirect (HL)
DD CB ii C6 SET 0,(IX+ii) Set bit 0, indexed (IX+ii)
FD CB ii C6 SET 0,(IY+ii) Set bit 0, indexed (IY+ii)
_
CB C7 SET 0,A Set bit 0 of register
CB C0 SET 0,B
CB C1 SET 0,C
CB C2 SET 0,D
CB C3 SET 0,E
CB C4 SET 0,H
CB C5 SET 0,L
_
CB CE SET 1,(HL) Set bit 1, indirect (HL)
DD CB ii CE SET 1,(IX+ii) Set bit 1, indexed (IX+ii)
FD CB ii CE SET 1,(IY+ii) Set bit 1, indexed (IY+ii)
_
CB CF SET 1,A Set bit 1 of register
CB C8 SET 1,B
CB C9 SET 1,C
CB CA SET 1,D
CB CB SET 1,E
CB CC SET 1,H
CB CD SET 1,L
_
CB D6 SET 2,(HL) Set bit 2, indirect (HL)
DD CB ii D6 SET 2,(IX+ii) Set bit 2, indexed (IX+ii)
FD CB ii D6 SET 2,(IY+ii) Set bit 2, indexed (IY+ii)
_
CB D7 SET 2,A Set bit 2 of register
CB D0 SET 2,B
CB D1 SET 2,C
CB D2 SET 2,D
CB D3 SET 2,E
CB D4 SET 2,H
CB D5 SET 2,L
_
CB DE SET 3,(HL) Set bit 3, indirect (HL)
DD CB ii DE SET 3,(IX+ii) Set bit 3, indexed (IX+ii)
FD CB ii DE SET 3,(IY+ii) Set bit 3, indexed (IY+ii)
_
CB DF SET 3,A Set bit 3 of register
CB D8 SET 3,B
CB D9 SET 3,C
CB DA SET 3,D
CB DB SET 3,E
CB DC SET 3,H
CB DD SET 3,L
_
CB E6 SET 4,(HL) Set bit 4, indirect (HL)
DD CB ii E6 SET 4,(IX+ii) Set bit 4, indexed (IX+ii)
FD CB ii E6 SET 4,(IY+ii) Set bit 4, indexed (IY+ii)
_
CB E7 SET 4,A Set bit 4 of register
CB E0 SET 4,B
CB E1 SET 4,C
CB E2 SET 4,D
CB E3 SET 4,E
CB E4 SET 4,H
CB E5 SET 4,L
_
CB EE SET 5,(HL) Set bit 5, indirect (HL)
DD CB ii EE SET 5,(IX+ii) Set bit 5, indexed (IX+ii)
FD CB ii EE SET 5,(IY+ii) Set bit 5, indexed (IY+ii)
_
CB EF SET 5,A Set bit 5 of register
CB E8 SET 5,B
CB E9 SET 5,C
CB EA SET 5,D
CB EB SET 5,E
CB EC SET 5,H
CB ED SET 5,L
_
CB F6 SET 6,(HL) Set bit 6, indirect (HL)
DD CB ii F6 SET 6,(IX+ii) Set bit 6, indexed (IX+ii)
FD CB ii F6 SET 6,(IY+ii) Set bit 6, indexed (IY+ii)
_
CB F7 SET 6,A Set bit 6 of register
CB F0 SET 6,B
CB F1 SET 6,C
CB F2 SET 6,D
CB F3 SET 6,E
CB F4 SET 6,H
CB F5 SET 6,L
_
CB FE SET 7,(HL) Set bit 7, indirect (HL)
DD CB ii FE SET 7,(IX+ii) Set bit 7, indexed (IX+ii)
FD CB ii FE SET 7,(IY+ii) Set bit 7, indexed (IY+ii)
_
CB FF SET 7,A Set bit 7 of register
CB F8 SET 7,B
CB F9 SET 7,C
CB FA SET 7,D
CB FB SET 7,E
CB FC SET 7,H
CB FD SET 7,L
_
CB 26 SLA (HL) Shift left, indirect (HL)
DD CB ii 26 SLA (IX+ii) Shift left, indexed (IX+ii)
FD CB ii 26 SLA (IY+ii) Shift left, indexed (IY+ii)
_
CB 27 SLA A Shift left register
CB 20 SLA B
CB 21 SLA C
CB 22 SLA D
CB 23 SLA E
CB 24 SLA H
CB 25 SLA L
_
ED 76 SLP Z180: Low power/sleep mode
_
CB 2E SRA (HL) Arith shift right, indirect (HL)
DD CB ii 2E SRA (IX+ii) Arith shift right, indexed (IX+ii)
FD CB ii 2E SRA (IY+ii) Arith shift right, indexed (IY+ii)
_
CB 2F SRA A Arithmetic shift right register
CB 28 SRA B
CB 29 SRA C
CB 2A SRA D
CB 2B SRA E
CB 2C SRA H
CB 2D SRA L
_
CB 3E SRL (HL) Shift right, indirect (HL)
DD CB ii 3E SRL (IX+ii) Shift right, indexed (IX+ii)
FD CB ii 3E SRL (IY+ii) Shift right, indexed (IY+ii)
_
CB 3F SRL A Logical shift right register
CB 38 SRL B
CB 39 SRL C
CB 3A SRL D
CB 3B SRL E
CB 3C SRL H
CB 3D SRL L
_
96 SUB (HL) Subtract from A, indirect (HL)
DD 96 ii SUB (IX+ii) Subtract from A, indexed (IX+ii)
FD 96 ii SUB (IY+ii) Subtract from A, indexed (IY+ii)
_
97 SUB A Subtract register from A
90 SUB B
91 SUB C
92 SUB D
93 SUB E
94 SUB H
95 SUB L
_
D6 nn SUB nn Subtract from A, immediate
_
ED 34 TST (HL) Z180: Test A, indirect (HL)
_
ED 3C TST A Z180: Test A against register
ED 04 TST B
ED 0C TST C
ED 14 TST D
ED 1C TST E
ED 24 TST H
ED 2C TST L
_
ED 64 nn TST nn Z180: Test A, immediate
_
ED 74 pp TSTIO pp Z180: Test A against port
_
AE XOR (HL) Exclusive OR A, indirect (HL)
DD AE ii XOR (IX+ii) Exclusive OR A, indexed (IX+ii)
FD AE ii XOR (IY+ii) Exclusive OR A, indexed (IY+ii)
_
AF XOR A Exclusive OR A with register
A8 XOR B
A9 XOR C
AA XOR D
AB XOR E
AC XOR H
AD XOR L
_
EE nn XOR nn Exclusive OR A, immediate