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Z8051H83.EXE
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Z180.H
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C/C++ Source or Header
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1993-05-21
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5KB
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122 lines
/*
* Z180, Z80 KIO and NCR 72C81 CGMA definitions
*
* Colin Weaver, HI-TECH Software April 1991
* Updated, May 1993
*/
#ifndef _Z180DEFS_
#define _Z180DEFS_ 1
#ifndef PORT
#define PORT static port unsigned char
#endif /* PORT */
/*
* Z80 KIO addresses
* (Default Setup for a Z84C90 KIO based at port address 0x0100)
*/
#ifndef KIOBASE
#define KIOBASE 0x100
#endif
PORT PIO_A_DATA @ KIOBASE+0x00; /* PIO port A */
PORT PIO_A_CMD @ KIOBASE+0x01;
PORT PIO_B_DATA @ KIOBASE+0x02; /* PIO port B */
PORT PIO_B_CMD @ KIOBASE+0x03;
PORT CTC0 @ KIOBASE+0x04; /* CTC channel 0 */
PORT CTC1 @ KIOBASE+0x05; /* CTC channel 1 */
PORT CTC2 @ KIOBASE+0x06; /* CTC channel 2 */
PORT CTC3 @ KIOBASE+0x07; /* CTC channel 3 */
PORT SIO_A_DATA @ KIOBASE+0x08; /* SIO channel A */
PORT SIO_A_CMD @ KIOBASE+0x09;
PORT SIO_B_DATA @ KIOBASE+0x0A; /* SIO channel B */
PORT SIO_B_CMD @ KIOBASE+0x0B;
PORT PIA_C_DATA @ KIOBASE+0x0C; /* PIA port C */
PORT PIA_C_CMD @ KIOBASE+0x0D;
PORT KIO_CMD @ KIOBASE+0x0E; /* KIO cmd register */
/*
* NCR 72C81 CRT controller addresses (6845 (CGA/MDA/HGC) compatible)
*/
PORT XCR @ 0x025A; /* extended control register */
PORT M1M2CR @ 0x025B; /* M1/M1 control register */
PORT altXCR @ 0x035A; /* alternate address for XCR */
PORT altM1M2CR @ 0x035B; /* alternate address for M1M2 */
PORT M_INDEX @ 0x3B4; /* 6845 index register */
PORT M_DATA @ 0x3B5; /* 6845 data register */
PORT M_MODE @ 0x3B8; /* mode control register */
PORT M_STATUS @ 0x3BA; /* CRT status register */
PORT M_MEMMODE @ 0x3BF; /* memory mode register */
PORT C_INDEX @ 0x3D4;
PORT C_DATA @ 0x3D5;
PORT C_MODE @ 0x3D8;
PORT C_COLOUR @ 0x3D9; /* colour select register */
PORT C_STATUS @ 0x3DA;
/*
* Z180 internal port addresses
*/
#ifndef IOB_180
#define IOB_180 0
#endif
PORT CNTLA0 @ IOB_180+0x00; /* ASCI control register A channel 0 */
PORT CNTLA1 @ IOB_180+0x01; /* ASCI control register A channel 1 */
PORT CNTLB0 @ IOB_180+0x02; /* ASCI control register B channel 0 */
PORT CNTLB1 @ IOB_180+0x03; /* ASCI control register B channel 0 */
PORT STAT0 @ IOB_180+0x04; /* ASCI status register channel 0 */
PORT STAT1 @ IOB_180+0x05; /* ASCI status register channel 1 */
PORT TDR0 @ IOB_180+0x06; /* ASCI transmit data reg, channel 0 */
PORT TDR1 @ IOB_180+0x07; /* ASCI transmit data reg, channel 1 */
PORT TSR0 @ IOB_180+0x08; /* Z180 ASCI receive data reg, channel 0 */
PORT RDR0 @ IOB_180+0x08; /* 64180 ASCI receive data reg, channel 0 */
PORT TSR1 @ IOB_180+0x09; /* Z80 ASCI receive data reg, channel 1 */
PORT RDR1 @ IOB_180+0x09; /* 64180 ASCI receive data reg, channel 0 */
PORT CNTR @ IOB_180+0x0A; /* CSI/0 control register */
PORT TRDR @ IOB_180+0x0B; /* CSI/0 transmit/receive data reg */
PORT TMDR0L @ IOB_180+0x0C; /* Timer data register, channel 0L */
PORT TMDR0H @ IOB_180+0x0D; /* Timer data register, channel 0H */
PORT RLDR0L @ IOB_180+0x0E; /* Timer reload register, channel 0L */
PORT RLDR0H @ IOB_180+0x0F; /* Timer reload register, channel 0H */
PORT TCR @ IOB_180+0x10; /* Timer control register */
PORT TMDR1L @ IOB_180+0x14; /* Timer data register, channel 1L */
PORT TMDR1H @ IOB_180+0x15; /* Timer data register, channel 1H */
PORT RLDR1L @ IOB_180+0x16; /* Timer reload register, channel 1L */
PORT RLDR1H @ IOB_180+0x17; /* Timer reload register, channel 1H */
PORT FRC @ IOB_180+0x18; /* Free running counter */
PORT SAR0L @ IOB_180+0x20; /* DMA source address reg, channel 0L */
PORT SAR0H @ IOB_180+0x21; /* DMA source address reg, channel 0H */
PORT SAR0B @ IOB_180+0x22; /* DMA source address reg, channel 0B */
PORT DAR0L @ IOB_180+0x23; /* DMA dest address reg, channel 0L */
PORT DAR0H @ IOB_180+0x24; /* DMA dest address reg, channel 0H */
PORT DAR0B @ IOB_180+0x25; /* DMA dest address reg, channel 0B */
PORT BCR0L @ IOB_180+0x26; /* DMA byte count reg, channel 0L */
PORT BCR0H @ IOB_180+0x27; /* DMA byte count reg, channel 0H */
PORT MAR1L @ IOB_180+0x28; /* DMA memory address reg, channel 1L */
PORT MAR1H @ IOB_180+0x29; /* DMA memory address reg, channel 1H */
PORT MAR1B @ IOB_180+0x2A; /* DMA memory address reg, channel 1B */
PORT IAR1L @ IOB_180+0x2B; /* DMA I/O address reg, channel 1L */
PORT IAR1H @ IOB_180+0x2C; /* DMA I/O address reg, channel 1H */
PORT BCR1L @ IOB_180+0x2E; /* DMA byte count reg, channel 1L */
PORT BCR1H @ IOB_180+0x2F; /* DMA byte count reg, channel 1H */
PORT DSTAT @ IOB_180+0x30; /* DMA status register */
PORT DMODE @ IOB_180+0x31; /* DMA mode register */
PORT DCNTL @ IOB_180+0x32; /* DMA/WAIT control register */
PORT IL @ IOB_180+0x33; /* Interrupt vector low register */
PORT ITC @ IOB_180+0x34; /* INT/TRAP control register */
PORT RCR @ IOB_180+0x36; /* Refresh control register */
PORT CBR @ IOB_180+0x38; /* MMU common base register */
PORT BBR @ IOB_180+0x39; /* MMU bank base register */
PORT CBAR @ IOB_180+0x3A; /* MMU common/bank area register */
PORT OMCR @ IOB_180+0x3E; /* Operation mode control register */
PORT ICR @ 0x3F; /* I/O base control register */
#endif /* _Z180DEFS_ */