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- From: altarrib@monk.ece.ucdavis.edu (Michael Altarriba)
- Newsgroups: comp.lsi,comp.lsi.cad,news.answers,comp.answers
- Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 2/4) [LONG]
- Supersedes: <lsi-cad-faq/part2_849196414@bird.ece.ucdavis.edu>
- Followup-To: comp.lsi.cad
- Date: 10 Jan 1997 00:53:30 GMT
- Organization: Department of Electrical and Computer Engineering, UC Davis
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- Approved: news-answers-request@MIT.Edu
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- Message-ID: <lsi-cad-faq/part2_852857606@bird.ece.ucdavis.edu>
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- Reply-To: clcfaq@ece.ucdavis.edu
- NNTP-Posting-Host: monk.ece.ucdavis.edu
- Summary: This is a biweekly posting of frequently asked questions with answers
- the for comp.lsi / comp.lsi.cad newsgroups. It should be consulted
- before posting questions to comp.lsi or comp.lsi.cad.
- Keywords: FAQ
- Xref: senator-bedfellow.mit.edu comp.lsi:7661 comp.lsi.cad:8483 news.answers:91630 comp.answers:23576
-
- Archive-name: lsi-cad-faq/part2
- Posting-Freqency: every 14 days
- Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html
-
- CADDY
- - Karlsruhe University, Germany
- - behavioral synthesis using VHDL as the input/output language, based on
- data-flow analysis; automated component selection (allocation), scheduling,
- and assignment. Different architechture styles are supported, such as
- multiplexers vs busses and two-phase vs single phase clocks.
- - Camposano, R.: "Synthesing Circuits From Behavioral Descriptions", IEEE
- Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989
- Rosenstiel, W., Kraemer, H.: "Scheduling and Assignment in High-Level
- Synthesis", in 'High-Level VLSI-Synthesis' R. Camposano, W. Wolf Ed.
- Kluwer, 1991
- Gutberlet P., Mueller J., Kraemer H., Rosenstiel W.: "Automatic Module
- Allocation in High-level Synthesis", Proc. of 1st EURO-DAC, 1992
-
- CALLAS
- - Siemens, Germany
- - highlevel, algortihmic and logic synthesis (contains CADDY, see
- above)
- - Koster, M. et al.: "ASIC Design Using the High-Level Synthesis
- System CALLAS: A Case Study", Proc. IEEE International Conference on
- Computer Design (ICCD '90), pp. 141-146, Cambridge, Massachusetts,
- Sept. 17-19, 1990
-
- CAMAD
- - Linkoping University, Sweden
- - scheduling, data path allocation and iteration from a Pascal subset
- - Peng, Z.: "CAMAD: A Unified Data Path/ Control Synthesis
- Environment", Proc. of the IFIP Working Conference on Design
- Methodologies for VLSI and Computer Architecture, pp. 53-67, Sept.
- 1988.
-
- CARLOS
- - Karlsruhe University, Germany
- - multilevel logic optimization for CMOS realizations
- - Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for
- CMOS Semi-Custom Integrated Circuits", IEEE Transactions on Computer-Aided
- Design, Vol 7, No 3, pp. 346-355, March 1988
-
- CATHEDRAL
- - Univ. of Leuve, Phillips and Siemens, Belgium
- - synthesis of DSP-circuits from algorithm descriptions
- - De Man, H.: "Architecture-Driven Synthesis Techiques for VLSI Implementation
- of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319,
- February 1990
-
- CATREE
- - Univ. of Waterloo, Canada
- - scheduling and data path allocation
- - Gebotys, C.H.: "VLSI Design Synthesis with Testability", Proc. of
- the 25th DAC, pp. 16-21, June 1988
-
- CHARM
- - AT & T Bell Labs., USA
- - data-path synthesis
- - Woo, N-S.: "A Global, Dynamic Register Allocation and Binding for a
- Data Path Synthesis System", Proc. of the 27th DAC, pp. 505-510, June 1990.
-
- CMU-DA (2)
- - Carnagie-Mellon University, USA
- - behavioral synthesis from ISPS
- - Thomas, D.: "Linking the Behavioral and Structural Domains of Representation
- for Digital System Design", IEEE Transactions on Computer-Aided Design, pp.
- 103-110, Vol. 6, No. 1, January 1987
-
- CONES
- - AT & T Bell Labs, USA
- - FSM synthesis, produces 2-level logic realizations (truth-table)
- - Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and
- programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara,
- Nov. 1986.
-
- DAGAR
- - University of Texas, Austin, USA.
- - scheduling and data-path allocation
- - Raj. V.K.: "DAGAR: An Automatic Pipelined Microarchitecture
- Synthesis System", Proc. of ICCD '89, pp. 428-431, October 1989.
-
- DELHI
- - IIT
- - design iteration, scheduling and data path allocation
- - Balakrishnan, M. et al.: "Integrated Scheduling and Binding: A
- Synthesis Approach for Design Space Exploration", Proc. of the 26th
- DAC, pp. 68-74, June 1989
-
- DESIGN AUTOMATION ASSISTANT (DAA)
- - AT & T Bell Labs, USA
- - expert system for data path synthesis
- - Kowalski, T.J. "The VLSI Desig Automation Assistant: An Architecture
- Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988
-
- ELF
- - Carleton University, Canada
- - scheduling and data path allocation
- - Girczyc, E.F. et al.: "Applicability of a Subset of Ada as an
- Algorithmic Hardware Description Language for Graph-Based Hardware
- Compilation", IEEE Trans. on CAD, pp. 134-142, April 1985.
-
- EUCLID
- - Eindhoven University of Technology, Netherlands
- - logic synthesis
- - Berkelaar, Michel R.C.M. and Theeuwen, J.F.M., "Real Area-Powe-Delay
- Trade-off in the EUCLID Logic Synthesis System" , proceedings of the Custom
- Integrated Circuits Conference 1990, Boston MA USA, pp 14.3.1 ff
-
- EXLOG
- - NEC Corporation, Japan
- - expert system, synthesizes gate level circuits from FDL descriptions
- - M. Watanabe, et al.,: "EXLOG: An Expert System for Logic Synthesis in
- Full-Custom VLSI Design", Proc. of 2nd Int. Conf. Application of Artificial
- Intelligence, August 1987.
-
- FACE/PISYN
- - General Electric, USA
- - FACE: high-level synthesis tools and a tool framework, PISYN:
- synthesis of pipelined architecture DSP systems (mostly)
- - Smith, W.D. et al.: "FACE Core Environment: The Model and it's
- Application in CAE/CAD Tool Development", Proc. of the 26th DAC, pp.
- 466-471, June 1989.
-
- FLAMEL
- - Stanford University, USA
- - data path and control-logic synthesis from Pascal description
- - Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions
- on Computer-Aided Design, Vol 6, No 2, March 1987.
-
- HAL
- - Carleton University, Canada
- - data path synthesis
- - Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of
- ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661,
- Vol. 8, No. 6, June 1989.
-
- HARP
- - NTT, Japan
- - scheduling and data path-allocation from FORTRAN
- - Tanaka, T. et al.: "HARP: Fortran to Silicon", IEEE Trans. on CAD,
- pp. 649-660, June 1989.
-
- HYPER
- - UCB, USA
- - synthesis for realtime applications (scheduling, allocation, module
- binding, controller design)
- - Chu, C-M. et al.: "HYPER: An Interactive Synthesis Environment for
- Real Time Applications", Proc. of ICCD '89, pp. 432-435, October 1989
-
- IMBSL/RLEXT
- - Univ. of Illinois, USA
- - data-path allocation, RTL-level design
- - Knapp D.W.: "Manual Rescheduling and Incremental Repair of Register
- Level Data Paths", Proc. of ICCAD '89, pp.58-61, November 1989.
-
- LSS (Logic Synthesis System)
- - IBM, USA
- - logic synthesis and optimization from many RTL-languages
- - Darringer, J. et al. "LSS: A System for Production Logic Synthesis",
- IBM Journal of Research and Developement, vol. 28, No. 5, pp. 272-280,
- Sept 1984.
-
- MAHA
- - University of Southern California, USA
- - data path synthesis
- - Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE
- Design Automation Conference, pp. 252-258, IEEE 1986.
-
- MIMOLA
- - University of Dortmund, Germany
- - scheduling, data-path allocation and controller design
- - Marwedel, P. "Matching System And Component Behavior in MIMOLA
- Synthesis Tools", Proc. of EDAC '90, pp. 146-156, March 1990.
-
- OLYMPUS/HERCULES
- - Stanford University, USA
- - behavioral synthesis from C-language (HERCULES), logic and physical
- synthesis
- - De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
- of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988
-
- SEHWA
- - University of Southern California, USA
- - pipeline-realizations from behavioral descriptions
- - Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
- Design Automation Conference, pp. 454-460, IEEE 1986.
-
- SIEMENS' SYNTHESIS SYSTEM
- - Siemens, Germany
- - partitioning, data path allocation and scheduling
- - Scheichenzuber, J. et al.: "Global Hardware Synthesis from
- Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
- June 1990.
-
- SIS (formerly MIS (II/MV))
- - University of California, Berkeley, USA
- - synthesis and verification system for sequential logic
- - E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai,
- A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton,
- A. Sangiovanni-Vincentelli: "SIS: A System for Sequential Circuit
- Synthesis", Tech report UCB/ERL M92/41, University of California,
- Berkeley, CA, May 1992
-
- SOCRATES
- - General Electric, University of Colorado, USA
- - expert system
- - logic optimization and mapping for different technologies
- - de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
- Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
- 1987.
-
- SPAID
- - Universty of Waterloo, Canada
- - DSP-synthesis for silicon compiler realizations
- - Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
- Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.
-
- SYNFUL
- - Bell-Northern Research, Canada
- - RTL and FSM synthesis for a production environment
- - G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
- Canadian Conference on Very Large Scale Integration, October 1990.
-
- SYSTEM ARCHITECT'S WORKBENCH
- - Carnagie-Mellon University, USA
- - behavioral synthesis
- - Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
- ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988
-
- UCB'S SYNTHESIS SYSTEM
- - UCB, USA
- - transformations, scheduling and data path allocation
- - Devadas, S.: "Algorithms for Hardware Allocation in Data Path
- Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89
-
- V COMPILER
- - IBM, USA
- - scheduling and data path allocation from V-language
- - Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
- and Test, pp. 8-17, April 1989.
-
- VSS
- - Univ. of California at Irvine, USA
- - transformations, scheduling and data path allocation from VHDL to
- MILO
- - Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
- October 1988.
-
- YORKTOWN SILICON COMPILER
- - IBM T.J.Watson Research Centre, USA
- - data path synthesis, logic synthesis etc.
- - Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
- pp. 204-311, Addison-Wesley, 1988
-
- 17: What free tools are there available, and what can they do?
-
- (This section can be viewed as a cross reference to the detailed descrip-
- tion of software that follows.)
-
- Analog VLSI and Neural Systems: Caltech VLSI CAD Tools
-
- Automated place and route: octtools, Lager
-
- Digital design environment: Galaxy CAD
-
- Lsi (polygon) schematic capture: magic, octtools(vem)
-
- Layout Verification: caltech tools (netcmp), gemini (Washington
- Univerity), wellchk (MUG)
-
- PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
- designs, of course :)
-
- Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
- switcap2.Synthesis: octtools, blis, Lager, item, (see section on synthesis)
-
- Standard schematic capture: PADS logic, PSPICE for windows
-
- 18: What Berkeley Tools are available for anonymous ftp?
-
- available from ftp://ic.eecs.berkeley.edu/pub
-
- adore: switched capacitor layout generator. (Requires Octtools 5.1 to
- compile.)
-
- bdd:
-
- road: analog layout router
-
- sis: simplifies both sum-of-products and generic multi-level boolean
- expressions; it includes many tools including espresso, bdd
-
- ext2spice: enhanced ext2spice for use with magic
-
- available from ftp://gatekeeper.dec.com/pub/misc
-
- espresso: simplifies sum-of-products boolean expressions
-
- 19: What Berkeley Tools are available through ILP?
-
- (From MUG 20 Contributed by Carol Block of U. C. Berkeley)
-
- A new version of the popular circuit simulator, Spice3F2, is now avail-
- able from the Industrial Liaison Program (ILP) Office at the University
- of California, Berkeley. A new release of Octtools will be forthcoming
- in 1993. Enclosed is a list of software distributed by this office.
-
- Adore, BBL.2, Berkeley Building-Block Layout System, Berkeley Computer
- Integrated Manufacturing System, Parameter Extraction Program for BSIM,
- Parameter Extraction for BSIM2, Bear-FP, Bert, BLIS, Spice 2G with BSIM
- Implementation, Cider, Ditroff/Gremlin, Ecstasy, EDIF 2 0 0, Elogic,
- ES1:Electrostatis 1-Dimensional Periodic Plasma, Franz Lisp, Glitter,
- IBC: Traveling-Wave-Tube Simulation, IEEE-754 Test Vector, Jsim, Jspice,
- Lanso, Magic-X11R3-Patch, Magic 1990 Decwrl/Livermore Release, Mahjong,
- Mighty, Octtools, Parmex Pix-Parmex, Plasma Device Simulation Codes, PLA
- Tools, Proteus, Ptolemy, Relax, Ritual, Sample, Sample-3D, Additional
- SAMPLE Documentation, Simpl-IPX and Simpl System 5, SIS, SPAM, Sparse,
- Spectre, Spice 2G6, Spice 3F2, Additional SPICE Documentation, Splat,
- Splice 3.0, Supercrystal, SWEC, Tempest, TimberWolf 3.2, Tsize, 1986 VLSI
- Tools, Wombat.
-
- Within a few weeks, a new catalog will be available via anonymous FTP.
- Users will also be able to obtain forms, ordering instruc- tions and some
- software via this means. Generally, recipients will have to com-
- plete an Agreement Form and pay a documentation and handling fee of about
- $250 per program.
-
- ILP can now distribute most of its programs in a variety of media,
- including: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK 50 (DEC tape for-
- mat), 9-track 1600 bpi and 9-track 6250 bpi. Visa and Mastercard ord-
- ers will be accepted on-line by 1993. Most of the software may be freely
- redistributed either within an organi- zation or to other organiza-
- tions, both within the United States and abroad, subject to the certain
- restrictions, including all U.S. Government restrictions, particu-
- larly those concerning ex- port.
-
- (from blurb+ftp, in the ILP distribution)
-
- If you have access to ftp, then the tape is free (you just get to suck it
- over by yourself) and you have to remember to print out the docs yourself
- too. The usual anonymous ftp rules:
-
- Name: ftp://ic.eecs.berkeley.edu/edif
- Address: 128.32.132.1
-
- |-EDIFWorld89.ps
- |-Release_7.6-notes-reversed.ps
- |-Release_7.6-notes.ps
- |-Release_7.6.tar.Z
- edif-|-agreement-reversed.ps
- |-agreement.ps
- |-agreement.tex
- |-assurance-reversed.ps
- |-assurance.ps
- |-assurance.tex
- |-blurb
- |-blurb+ftp
-
- Other Ports
- -------------------------------------------------------------------- I
-
- I have a port of the system for SysV, Apollo and HP machines as well
- which is available on request. Most of these operating systems are
- mature enough now to work directly with Release 7.6. The system has been
- ported to other non-Unix machines such as VMS, the mac, and various main-
- frame architectures; these latter being a nontrivial effort on the part
- of the individuals involved, but it was accomplished. I do not have
- these ports; I just know that they are possible because they have been
- performed by others.
-
- For additional information, contact:
-
- Industrial Liaison Program
- 205 Cory Hall
- Software Distribution Office
- University of California at Berkeley
- Berkeley, CA 94720
-
- TEL: (510) 643-6687
- FAX: (510) 643-6694
- ilpsoftware@eecs.berkeley.edu
-
- 20: Berkeley Spice (Current version 3f4)
-
- (From spice_info on ic.eecs.berkeley.edu)
-
- Upgrading from Spice 3f2 to 3f4
-
- The current version is 3f4. This is derived from version 3f2 by applying
- a patch. The patch is available via ftp from ic.eecs.berkeley.edu.
-
- Acquiring Spice 3f2
-
- For more information on how to acquire Spice3f2, please send your physi-
- cal mailing address to "ilpsoftware@eecs.berkeley.edu" and request a
- software catalog. This will give you all of the necessary information
- for ordering Spice3f2 and other Berkeley CAD software, including an order
- form and use agreements. At last check, the cost for spice3f2 was
- $250.00 (this price may change without notice).
-
- Systems supported and Formats Supplied
-
- Spice3f2 has been compiled on the following systems:
- Ultrix 4, RISC or VAX
- SunOS 4, Sun3 or Sun4
- AIX V3, RS/6000
- HP-UX 8.0, 9000/700
- MS-DOS on the IBM PC, using MicroSoft C 5.1 or later
-
- The following systems have been successfully tested either in the past or
- by someone outside of UC Berkeley.
-
- Dynix 3.0, Sequent Symmetry or Balance (does _not_ take advantage of
- parallelism)
- HP-UX 7.0, 9000/300
- Irix 3.2, SGI Personal Iris
- NeXT 2.0
- Apple MacIntosh, Using Think C
-
- Spice3f2 is distributed in source form only. The C compiler "gcc" has
- been used successfully to compile spice3f2, as well as the standard com-
- pilers for the systems listed above.
-
- Spice3 displays graphs under X11, PostScript, or a graphics-terminal
- independent library, or as a crude, spice2-like line-printer plot. On
- the IBM PC, CGA, EGA, and VGA displays are supported through the Micro-
- Soft graphics library. Note in particular that there is no Suntools
- interface.
-
- Note the the X11 interface to Spice3 expects release 4 or later, and
- requires the "Athena Widgets Toolkit" ("Xaw") which may be available only
- in the "unsupported" portion of your vendor software. A version of
- "OpenWindows" has problems due to undefined routines during linking --
- linking with a null copy of these routines has reportedly worked, but
- "OpenWindows" has not been tested in any way for this release.
-
- Note that for practical performance a math co-processor is required for
- an IBM PC based on the 286 processor. A math co-processor is also recom-
- mended for the more advanced IBM PC systems.
-
- (from posting to comp.lsi.cad) The Windows NT port of spice3e2, Spice32,
- is available via ftp from site
- ftp://ftp.cica.indiana.edu/pub/pc/win3/nt/spice100.zip . A similar port
- of nutmeg is included.
-
- (from Robert Zeff <robert@koko.csustan.edu>)
-
- I have revised my on line help for Spice32 / Nutmeg32 for Windows NT and
- Win3.1 to Berkeley's version 3F4. It is available by ftp from
- ftp://csustan.csustan.edu/pub/spice/nutmeg.hlp . I have removed the exe-
- cutables for DOD complience. For access, see the readme file in that
- directory.
-
- I've updated my Spice circuit simulator to 3F5 and have included the
- BSIM3v3 level 8 mosfet model. You can get it at
-
- http://sonnet.com/rzeff
-
- Sometime it will also be available (ftp) at
- csustan.csustan.edu/pub/spice/i386 or www.zapco.com Yes, it does work on
- Win95.
-
- The Unix distribution comes on 1/2" 9-track tape in "tar" format, TK50
- tape (DEC tape), or QIC-150 1/4" cartridge tape (Sun cartridge tape).
- The MS-DOS distribution comes on several 3.5" floppy diskettes (both high
- and low density) in the standard MS-DOS format. The contents of both
- distributions are identical, including file names.
-
- New features in 3f2
-
- The following is a list of new features and fixes from the previous major
- release of Spice3 (3e.2) (see the user's manual for details):
-
- AC and DC Sensitivity.
- MOS3 discontinuity fix ("kappa").
- Added a new JFET fitting parameter.
- Minor initial conditions fix.
- Rewritten or fixed "show" and "trace" commands.
- New interactive commands "showmod" and "alter".
- Minor bug-fixes to the Pole-Zero analysis.
- Miscellaneous bug fixes in the front end.
-
- Additional features since release 3d.2 are:
- Lossy transmission line model (not available under MS-DOS).
- Proper calculation of sheet resistance in MOS models.
- A new command ("where") to aid in debugging troublesome
- circuits.
- Smith-chart plots improved.
- Arbitrary sources in subcircuits handled correctly.
- Arbitrary source reciprocal calculations and DC biasing
- now done correctly.
- Minor bug-fixes to the Pole-Zero analysis.
- Miscellaneous bug fixes in the front end.
-
- A Note on Version Numbering
-
- Spice versions are numbered "NXM", where "N" is a number representing the
- major release (as in re-write), "X" is a letter representing a feature
- change reflected by a change in the documentation, and "M" is a number
- indicating a minor revision or bug-patch number.
-
- FTP Access and Upgrades
-
- There is no anonymous ftp access for the Spice3 source(see below). The
- manual for spice3f2 (in it's postscript format) is available via
- anonymous ftp from ftp://ic.eecs.berkeley.edu/pub/spice3/um.3f.ps . If
- you are interested in the troff/me source, contact the email address
- below (the "make" files and whatnot are somewhat cumbersome for the
- manual).
-
- Patches or upgrades for Spice3 are _not_ normally supplied, however we
- have made exceptions to this rule, particularly in the case of minor ver-
- sion changes (such as 3f2 to 3f3).
-
- Email Address for Problems
-
- Please direct technical inquiries to "spice@berkeley.edu" or "spice-
- bugs@berkeley.edu" (for now these addresses are the same), and ordering
- or redistribution queries to "ilpsoftware@eecs.berkeley.edu". If you
- find that your email to "spice" or "spice-bugs" doesn't get a response in
- a few days, resend your message.
-
- (from Jim Nance <jlnance@isscad.com>)
-
- Hello all circuits people. I have uploaded source and binaries for Spice
- 2g6 to ftp://sunsite.unc.edu/pub/Linux/Incoming/spice2g6.tar.z . As you
- are probably aware, spice is a circuit simulator, written at Berkeley.
- Version 2g6 was released in 1983. The current Berkeley version is
- approximatly Spice 3f2, however, Berkeley does not want this distributed.
- Source code for Spice 3e2 did escape from Berkeley and was ported to
- Linux (and a lot of other platforms). This code has been removed from
- anonymous FTP servers, and is therefore no longer available. Berkeley
- does publish the source code for Spice 2g6.
-
- I obtained the source code for Spice from a 386BSD ftp site. The code
- compiled cleanly, with only minor changes to the Makefile being required.
- I also included an ASCII spice manual which I have found helpful.
-
- (from Martin Maschmann <martin.maschmann@t-online.de>)
-
- I can also be reached at <martin.maschmann@vlsi.com>
-
- I have created a SCHEMATIC CAPTURE program running under X11Rsomething
- (something >=5) for both linux, sunos and SOLARIS. SPICECAD now has a
- home page which has the URL:
-
- <URL:http://home.t-online.de/home/martin.maschmann>
-
- There you will find some links to an ftp site from where you can download
- the compiled binaries. Before loading, you can look at some pictures
- which show how the graphics interface looks like. If you don't like it,
- don't load it.
-
- An english manual is included. Please read the manual! Example schemat-
- ics are included, too.
-
- Soure code is not included, because the making of SPICECAD means making
- of SPICE3F4 , which is hard-linked to SPICECAD, making a stripped version
- of GNUPLOT and making the schematic entry part.
-
- All in all, it is really a mess, especially if you look at the schematics
- part which is VERY hard to understand.
-
- Customizing SPICECAD for your own needs means: send me a mail which
- explains the problem, and then I can tell you whether I will do it by
- myself (because there could be a wide need for this new feature), or
- whether you can do it by yourself.
-
- For example, if you want to create an interface for a new simulator (a
- PSPICE interface is still missing, an HSPICE interface will be available
- in the future), I can send you several example files (the interface for
- HSPICE), and you write the interface. Finally , everything can be linked.
-
- Those who want to add some features I cannot write (because my program-
- ming skills and time is limited) can obtain the source code on a small
- QIC cartridge. What I am thinking of is an EDIF interface. This would be
- a very nice feature.
-
- 21: Octtools (Current version 5.1)
-
- (From the ANNOUNCE-5.1 that comes with it)
-
- Octtools is a collection of programs and libraries that form an
- integrated system for IC design. The system includes tools for PLA and
- multiple-level logic synthesis, state assignment, standard-cell, gate-
- matrix and macro-cell placement and routing, custom-cell design, circuit,
- switch and logic-level simulation, and a variety of utility programs for
- manipulating schematic, symbolic, and geometric design data. Most tools
- are integrated with the Oct data manager and the VEM user interface.
-
- The software requires UNIX, the window system X11R4 including the Athena
- Widget Set. The design manager VOV and a few other tools require the C++
- compiler g++.
-
- Octtools-5.1 have been built and tested on the following combinations of
- machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
- and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
- and Sun SparcStation running OS 4.0. The program has been tried on the
- following machines, but is not supported: Sequent Symmetry, IBM RS/6000
- running AIX 3.1.
-
- To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
- and a printed copy of the documentation) for a $250 distribution charge,
- see section on Berkeley ILP.
-
- Questions may be directed to octtools@ic.eecs.berkeley.edu.
-
- 22: Ptolemy (Current version 0.5):
-
- (From comp.lsi.cad)
-
- What is Ptolemy:
- ---------------
-
- Ptolemy provides a highly flexible foundation for the specification,
- simulation, and rapid prototyping of systems. It is an object oriented
- framework within which diverse models of computation can co-exist and
- interact. For example, using Ptolemy a data-flow system can be easily
- connected to a hardware simulator which in turn may be connected to a
- discrete-event system, etc. Because of this, Ptolemy can be used to
- model entire systems.
-
- Ptolemy also has code generation capabilities. From a flow graph
-
- description, Ptolemy can generate C code and DSP assembly code for rapid
- prototyping. Ptolemy can also generate Silage and VHDL descriptions for
- hardware synthesis.
-
- Ptolemy has been used for a broad range of applications including signal
- processing, telecomunications, parallel processing, wireless communica-
- tions, network design, radio astronomy, real time systems, and
- hardware/software co-design. Ptolemy has also been used as a lab for
- signal processing and communications courses. Currently Ptolemy has hun-
- dreds of users in over 100 sites, both in industry and academia.
-
- Ptolemy is available for the Sun 4 (sparc), DecStation (MIPS), and HP
- (HP-PA) architectures. Installing the system requires 90 Mbytes for
- Ptolemy (more if you optionally remake). Ptolemy also requires at least
- 8 Mbytes of physical memory.
-
- Getting the New Release:
- -----------------------
-
- Ptolemy is available via anonymous ftp at:
- ftp://ptolemy.eecs.berkeley.edu/pub/README This site contains the entire
- Ptolemy distribution, a postscript version of the Ptolemy manual, and
- several Ptolemy papers.
-
- For those unfamiliar with anonymous ftp, here's what you need to do:
- 1. FTP to Internet host "ptolemy.eecs.berkeley.edu" (128.32.240.78)
- 2. Login as "anonymous"; use your full email address as the password
- 3. cd pub
- 4. get the README file and follow its instructions.
-
- Organizations without Internet FTP capability can obtain Ptolemy
- without support from ILP:
-
- EECS/ERL Industrial Liaison Program Office
- Software Distribution
- 205 Cory Hall
- University of California, Berkeley
- Berkeley, CA 94720
- (510) 643-6687
- email: ilpsoftware@eecs.berkeley.edu
-
- This includes printed documentation, including installation instructions,
- a user's guide, and manual pages. A handling fee (on the order of $250)
- will be charged.
-
- 23: Lager (Current version 4.0):
-
- (From MUG 18)
-
- The LAGER system is a set of CAD tools for performing parameterized VLSI
- design with a slant towards DSP applications (but not limited to DSP
- applications). A standard cell library, datapath library, several module
- generators and several pad libraries comprise the cell library. These
- tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
- sippi State, and ITD. The tool development has been funded by DARPA
- under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
- ley). LAGER 3.0 was described in MUG 15.
-
- Send email to reese@erc.msstate.edu if you are interested in obtaining
- the toolset via FTP. If you cannot get the distribution via ftp then send
- one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
- by phone at (601)-325-3670 or at one of the following addresses:
-
- (US Mail Address)
- P.O. Box 6176
- Mississippi State, MS 39762
-
- (FEDEX)
- 2 Research Boulevard
- Starkville, MS 39759
-
- Be sure to include a return FEDEX waybill we can use to ship your tape
- back to you. Instead of sending a tape and FEDX waybill, you can also
- just send us a check for $75 and we will send you back a tape. Make the
- check payable to Mississippi State Univ. The tape will be written on a
- high density tape drive (150 Mb). Older low density SUN tape drives (60
- Mb) cannot read this format so you need to have access to one of SUN's
- newer tape drives.
-
- 24: BLIS (Current version 2.0):
-
- (From their announcement posted here)
-
- BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
- synthesis of digital circuits from high-level descriptions. Version 2.0
- supports functional-level synthesis starting from the ELLA hardware
- description language. Other languages can easily be supported by inter-
- facing a parser to the internal data-flow representation of BLIS.
-
- BLIS is distributed through the Industrial Liason's Program (ILP) Office
- of the UCB EECS department. The cost of $250 covers media and distribu-
- tion charges. Binaries are provided for SUN4 and DEC MIPS architectures
- but BLIS should compile on most other machines supported by the GNU C and
- C++ compilers (e.g. HP, vax, etc). ELLA language documentation and simu-
- lator are not supplied with the BLIS distribution, but can be obtained
- from Computer General.
-
- 25: COSMOS and BDD
-
- (From their announcement posted here)
-
- Obtaining and installing COSMOS and BDD.
-
- The COSMOS package generates switch-level simulators for MOS circuits.
- The BDD package is a subset of COSMOS providing a set of library routines
- for symbolic Boolean manipulation.
-
- To obtain a copy of either COSMOS or BDD via FTP:
-
- 1. Create an appropriate subdirectory. For COSMOS, you may want to
- create a symbolic link /usr/cosmos to this directory, although this is
- not essential.
-
- 2. Connect to the subdirectory
-
- 3. FTP to ftp://n3.sp.cs.cmu.edu/usr/cosmos/ftp (login anonymous, pass-
- word yourname@your.host.name)
-
- 4. Type:
-
- cd /usr/cosmos/ftp
- ls
-
- 5. Select which version of the code you want. The files are named
- bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver-
- sion number. Generally you should select the highest numbered ver-
- sion.
-
- 6. 6. Type:
- get <FILE> (where <FILE> is the file name of the selected ver-
- sion).
- get README
- quit
-
- 7. Follow the instructions in README
-
- 8. Send the following information to cosmos@cs.cmu.edu
-
- Your name
- Your postal address
- Your net address
- The file retrieved
- The date of your retrieval
-
- COSMOS and BDD are made available with the understanding that no part of
- it will be redistributed further without permission.
-
- Last updated 18 July 1991 by Derek Beatty.
-
- 26: ITEM
-
- (Taken from the item.news file contained in the package:)
-
- The first public release of ITEM, UCSC's logic minimizer using if-then-
- else DAGs, was made 2 January 1991. The system is available by anonymous
- ftp from ftp://ftp.cse.ucsc.edu/pub/item/item.tar.Z . Also available are
- tech reports about the algorithms and data structures (88-28, 88-29, and
- 90-43).
-
- ITEM can also be found at ftp://ftp.cse.ucsc.edu/pub/item directory.
-
- 27: PADS logic/PADS PCB:
-
- While this is a commercial product, they have just recently made avail-
- able a shareware version. This version is fully functional and indenti-
- cal to their schematic capture and PCB autoplace and route software
- except that it is limited to about 50 components. It is available for
- IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
- several sites including
- <URL:ftp://wuarchive.wustl.edu:/systems/ibmpc/simtel/cad/pads*.zip>.
- There is a $50 registration fee if you would like to get future updates
- from them.
-
- 28: Another PCB Layout Package:
-
- (from Randy Nevin <randyn@microsoft.com>:)
-
- I am distributing a freely-copyable printed circuit board (pcb) autorout-
- ing software package called PCBCAD. It runs on PC-compatible computers,
- and requires EGA resolution. All source code is included. It contains: a
- "ratnest" viewer, autorouters for 1- and 2-layer boards, a board viewer,
- hard copy output programs for hp laserjet and postscript printers, and a
- DXF converter (autocad). For more background on autorouting, see the
- related article published in the September 1989 Dr. Dobb's Journal. In a
- nutshell, what you do is create an ascii file which describes your cir-
- cuit, feed it to the autorouter, and the circuit will be routed for you.
- To receive the programs, send a stamped, self-addressed floppy mailer and
- a floppy to:
-
- Randy Nevin,
- 24135 SE 16th PL
- Issaquah, WA 98029, USA
- internet: randyn@eskimo.com.
-
- The programs are also available via ftp from
-
- <URL:ftp://oak.oak.and.edu/SimTel/msdos/cad/pcbca110.zip>
- <URL:ftp://oak.oak.and.edu/SimTel/msdos/cad/pcbcattl.zip>
-
- 29: Magic (Current version 6.5):
-
- This is a polygon based lsi layout editor. It is capable of reading and
- writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
- and cif. It is available for anonymous ftp from
- ftp://gatekeeper.dec.com/pub/DEC/magic .
-
- Linux versions of magic are available from the standard linux mirror
- archives, such as ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/
- [128.6.18.15]:
-
- ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/magicp3-src.tar.gz
- ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/magic63p3-run.tar.gz
-
- A short summary of the problems people have experienced in using Magic
- 6.3 under Linux is available:
-
- ftp://magnet.fsu.edu/users/murali/magic6.3-summary
-
- (from Bob Mayo <mayo@pa.dec.com>)
-
- Magic 6.4 is a minor update of magic. It includes the patches from the
- 6.3 notes series, as well as ports to Digital's Alpha AXP OSF/1 worksta-
- tions (courtesy of Stefanos Sidiropoulos) and to Linux on a PC (courtesy
- of Harold Levy).
-
- This release includes an updated copy (version 9.2) of Stanford's Irsim
- program, as well as scmos tech files (version 8.0.0) from MOSIS.
-
- The easiest way to get magic is via the World Wide Web:
-
- <URL:http://www.research.digital.com/wrl/magic/magic.html>
-
- If you don't have web access, use anonymous FTP from gatekeeper.dec.com
- in the directory pub/DEC/magic/6.4. This directory also include the file
- irsim-9.2.tar.Z.
-
- (from Tom Burd <burd@eecs.berkeley.edu>)
-
- If you have layout you can extract, try using irsim-cap, a modified ver-
- sion of irsim. switched level simulation gives results close to spice
- (within 20% for certain (rail-to-rail) circuits... CMOS, nora, domino,
- etc. stuff like CPL, some differential logic styles, etc. gives irsim
- problems in its estimation). And it is _much_ faster than SPICE. We
- simulate upwards of 100k xsistor chips, but it takes a good CPU and lots
- of memory. You can download
- such:<URL:ftp://infopad.eecs.berkeley.edu/pub/irsim-cap.tar.Z>
-
- (from comp.lsi.cad)
-
- Newer versions of magic (6.5) and irsim (9.4) are now available through
- the magic web page:
-
- <URL:http://www.research.digital.com/wrl/projects/magic/magic.html>
-
- Magic 6.5 is yet another upgrade of magic. It includes all patches posted
- since the introduction of 6.4.4 and integrates ports to Solaris and
- Free-BSD. Additionally it includes:
-
- New versions of ext2sim and ext2spice.
- Cif/Calma enhancements
- DRC enhancements
- Some new commands.
- The latest version of the mosis technology file.
-
- Magic-6.5 is distributed with irsim-9.4. This new version deals with the
- sim file format produced by magic-6.5 and it also includes support for
- power estimation and writing user modules in C.
-
- The system has been compiled and tested in a number of systems (solaris,
- irix, ultrix, linux, sunos, hpux to name a few). However the usuall dis-
- claimers about the no-maintenance mode apply: I can't promise that I will
- fix any bugs (which I am sure that exist) but I will do my best.
-
- Comments and bug reports/patches should be posted to the magic hypermail
- archive: magic-hypermail@pa.dec.com
-
- 30: PSpice:
-
- This is a commercial product, however, they do have a student version
- that is available (limited to around 16 transistors).
-
- PC dos version 5.0a:
- ftp://oak.oakland.edu/pub/msdos/electric/pspice5a.zip
- ftp://oak.oakland.edu/pub/msdos/electric/pspice5b.zip
-
- PC windows3 version 5.1:
- ftp://ftp.cica.indiana.edu/pub/pc/win3/util/pspice1.zip
- ftp://ftp.cica.indiana.edu/pub/pc/win3/util/pspice2.zip
-
- Mac version 5.1:
- ftp://sumex-aim.stanford.edu/info-mac/app/pspice-51.hqx
-
- The PC version is also available at a number of U.S. and non-U.S. sites.
-
- PSPICE 6.0
-
- (from Jonathan Layes <layes@qucis.queensu.ca>)
-
- An evaluation version of PSpice 6.0 for DOS and Windows 3.1 is now avail-
- able.
-
- PC dos version 6.0:
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d1.zip>
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d2.zip>
-
- PC windows3.1 version 6.0:
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w1.zip>
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w2.zip>
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w3.zip>
-
- PC explode disk:
- <URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6ed.zip>
-
- The incoming directory is not directly readable, but files can still be
- read via FTP. These will be moved ot a more appropriate directory, prob-
- ably pub/cookbook/softw/msdos.
-
- PSPICE 6.2
-
- (from Richard Nekus<ao387@freenet.carleton.ca>)
-
- Evaluation versions of the circuit simulator and schematic editor are
- available with the following limitations:
-
- These device limitations apply:
-
- - 64 analog nodes
- - or, 10 transistors (any combinationn of B, M, Q, or J devices)
- - or, 2 opamps
- - or, 10 transmission lines (up to 4 coupled)
- - or, 65 digital primitive devices
- - or, logic output transitions limited to 10000
- - or, logic expression primitives limited to 36 I/O pins
- - or, any combination of the above (which will result in a
- lower allowable number of each)
-
- Additional limitations include:
-
- - device characterization for diodes only
- - stimulus generation for sine waves only
- - libraries with approximately 22 analog and 140 digital parts
- - synthesis of up to 3rd order filters
-
- Schematic Editor limitations include:
-
-