home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
Magazyn Enter 1999 January
/
enter_01_1999_2.iso
/
BIOS
/
ctchip34
/
UM881.CFG
< prev
next >
Wrap
Text File
|
1995-10-03
|
6KB
|
193 lines
;**********************************************************
NAME=UM82C881; (UMC, 486PCI)
;**********************************************************
ConfigAccess=1
MACRO OPEN =0CFBh:xxxxxxx1,0CFAh:00000000
MACRO CLOSE=0CFBh:xxxxxxx0
MODE=INDEX32 ;; alle Zugriffe 32bittig
INDEXPORT=0CF8h ;; CONFADDR
DATENPORT=0CFCh ;; CONFDATA
BASEADR=80008000h
*IF 0:==$FFFF
WRITELN "CONFIGAccess 1 nicht implementiert"
MODE=DIRECT
ConfigAccess=0
MACRO OPEN=0CF8h:1111xxxx,0CFAh:00000000
MACRO CLOSE=0CF8h:0000xxxx,0CFAh:00000000
BASEADR=C000h
*IF 0:==$FFFF
WRITELN "CONFIGAccess 0 nicht implementiert"
EXIT "Abbruch"
*ELSE
WRITELN "CONFIGAccess 2 implementiert"
*ENDIF
*ELSE
WRITELN "CONFIGAccess 1 implementiert"
*ENDIF
MACRO UMC = 0:==$1060
MACRO um82C881 = UMC, 2:==$8881
*IF UM82C881
WRITELN UMC-UM82C881
*ELSE
EXIT Chipsatz unbekannt
*ENDIF
MACRO CACHEOFF = 56h:00000000, flush, 57h:01000000
MACRO CACHEON = 56h:00000000, flush, 57h:00000000
MACRO L2OFF = Cacheoff, 50h:0xxxxxxx,Cacheon
MACRO L2ON = 50h:1xxxxxxxx,Flush,50h:1xxxxxxxx
MACRO L1OFF = CDNW:=11, WBINVD ;; Bits CD und NW in CR0 auf 1
MACRO L1ON = CDNW:=00, WBINVD ;; Bits CD und NW in CR0 auf 1
MACRO L2WB = L2OFF, Flush, 50h:01xxxxxx, L2ON
MACRO L2WT = L2OFF, Flush, 50h:00xxxxxx, L2ON
MACRO L2Dirty = L2OFF, Flush, 51h:xxxxxx0, L2ON
MACRO L2NoDirty = L2OFF, Flush, 51h:xxxxxx1, L2ON
;**********************************************************
INDEX16=0 ; VID PCI Vendor Identification r/o
;**********************************************************
BIT=15..00 ; Vendor Identification
$8086= INTEL
$1060= UMC
else = other Vendor
;**********************************************************
INDEX16=2 ;DID PCI Divice Identification r/o
;**********************************************************
BIT=15..00 ; Device Identification
$04A3= Mercury/Neptun
else= unknown
;**********************************************************
INDEX16=4 ; PCICMD PCI Command Register r/w
;**********************************************************
BIT=15..09 ; Reserved
BIT=08 ;0/1 SERRE
BIT=06 ;0/1 Parity Error (Master Enable)
BIT=02 ;0/1 Bus Master Operations
BIT=01 ;0/1 Memory Access
BIT=00 ;0/1 I/O-Access
;**********************************************************
INDEX16=6h ; PCISTS PCI Status Register (r/w)
;**********************************************************
BIT=15 ;reserved
BIT=14 ;Signaled System Error
BIT=13 ;Received Master Abort Status
BIT=12 ;Received Target Abort Status
BIT=11 ;reserved
BIT=10,09 ;DevSel
00=FAST
01=Medium
10=SLOW
11=reserved
BIT=08 ;Data Parity
0= not detected
1= detected
;**********************************************************
INDEX=8 ;RID Revision IDentification Register r/o
;**********************************************************
BIT=7..0 ;PCI Cache/Memory-Controller
0000xxxx= Mercury 82434LX
0001xxxx= Neptun 82434NX
xxxx0001= A1-Step
xxxx0010= A2-Step
xxxx0011= A3-Step
;**********************************************************
INDEX=9 ;RLPI Register-Level Programming Interface r/o
;**********************************************************
BIT=7..0
00=no register-level Programming Interface
;**********************************************************
INDEX=0Ah ;SUBC Sub-Class-Code r/o
;**********************************************************
BIT=7..0
00=PCMC is host Bridge
;**********************************************************
INDEX=0Bh ;BASEC Base Class Code r/o
;**********************************************************
BIT=7..0
$06=PCMC is Bridge Device
;**********************************************************
INDEX=0Dh ; MLT Master Latency Timer Register r/w
;**********************************************************
BIT=7654 ;Master Latency Timer, bus clocks = 16 x this value
;**********************************************************
INDEX=0Fh ;BIST BIST-Register r/o
;**********************************************************
BIT=7 ;0/1 BIST (ro), not supported by 82434LX/NX
BIT=6 ;Start BIST (r/w), not supported by 82434LX/NX
BIT=3..0 ;Completion Code (ro)
;**********************************************************
INDEX=50h ;L2 Cache Control Register
;**********************************************************
BIT=7 ;0/1 L2_Cache
BIT=6 ;Cache-Policy
0=Write Thru
1=Write Back
BIT=54 ;Cache Speed
00= Read 3-2-2-2/ Write 3T
01= Read 3-1-1-1/ Write 3T
10= Read 2-2-2-2/ Write 2T
11= Read 2-1-1-1/ Write 2T
BIT=3 ;Cache Banks
0=1 Bank
1=2 Banks
BIT=210 ;Cache Size
000=0KB
001=64KB
010=128KB
011=256KB
100=512KB
101=1MB
11x=2MB
;**********************************************************
INDEX=51h ;Wait State Control
;**********************************************************
BIT=76 ;DRAM Read Speed
00=3 Waits
01=2 Waits
10=1 Wait
11=0 Waits
BIT=54 ;DRAM Write Speed
00=3 Waits
01=2 Waits
10=1 Wait
11=0 Waits
BIT=3 ;0/1 Resource Lock Enable
BIT=2 ;Graphic Adaptor
0=VL Bus
1=PCI Bus
BIT=1 ;L1 Write Back Policy
0=Write Back
1=Write Thru
BIT=0 ;L2 Cache Tag length
0=7 Bits
1=8 Bits
;**********************************************************
INDEX=52h ;DRAM Configuration Register
;**********************************************************
BIT=7 ;Host-to-PCI Post Write
0=1 Wait State
1=0 Wait States