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Microsoft Windows Help File Content  |  1993-06-10  |  18KB  |  434 lines
  1. ;**************************************************************
  2. ;SYMPHONY HAYDN, System: SL82C461, Bus: SL82C362 in SYM486.CFG
  3. ;**************************************************************
  4. INDEXPORT=A8h    ; alternativ A2h
  5. DATENPORT=A9h    ; alternativ A3h
  6. ;**************************************************************
  7. ; SL82C461
  8. ;**************************************************************
  9. ;**************************************************************
  10. INDEX =0         ; CHIP Control
  11. ;**************************************************************
  12. BIT=7            ;WT3167 existence (ro)
  13.                  0=non existing
  14.                  1=existing
  15. BIT=6            ;0/1 Cachemode   (ro)
  16. BIT=5            ;CPU-TYP        (ro)
  17.                  0=486
  18.                  1=386DX
  19. BIT=4            ;CPU ID (if 386)          (ro)
  20.                  0=386SX
  21.                  1=386DX
  22. BIT=3            ;80387 existence (ro)
  23.                  0=non existing
  24.                  1=Existing
  25. BIT=2            ;80387 Ready Source (if 386)
  26.                  0=from 80387
  27.                  1=from SL82C461
  28. BIT=1            ;0/1 8042 RC emulation
  29. BIT=0            ;Configuration Port address
  30.                  0=A8h/A9h (default)
  31.                  1=A2h/A3h
  32. ;**************************************************************
  33. INDEX =1         ; ROM Control
  34. ;**************************************************************
  35. BIT=7            ;ROM Data width (ro)
  36.                  0=8 bit
  37.                  1=16 bit
  38. BIT=65           ;ROM Waitstates
  39.                  00=reserved
  40.                  01=1 wait
  41.                  10=2 waits
  42.                  11=3 waits
  43. BIT=43           ;high/middle boot ROM disable
  44.                  00=enable high/middle Boot ROM
  45.                  x1=disable middle Boot ROM
  46.                  1x=disable high Boot ROM
  47. BIT=2            ;0/1 Combined BIOS (ro)
  48. BIT=1            ;0/1 Gate A20 emulation
  49. BIT=0            ;0/1 Fast GateA20
  50. ;**************************************************************
  51. INDEX =2         ; Clock Control
  52. ;**************************************************************
  53. BIT=7            ;0/1 SLOW MODE
  54. BIT=65           ;Slow speed selection for CCLK2
  55.                  00=CLK2/4  (default)
  56.                  01=CLK2/16
  57.                  10=BCLK
  58.                  11=reserved
  59. BIT=432          ;BCLK speed selection
  60.                  000=CLK2/3
  61.                  001=CLK2/4 (default)
  62.                  010=CLK2/5
  63.                  011=reserved
  64.                  100=CLK2/6
  65.                  101=CLK2/4
  66.                  110=CLK2/2.5
  67.                  111=CLK2/2
  68. BIT=1            ; must be 0
  69. BIT=0            ; reserved must be 1
  70. ;**************************************************************
  71. INDEX=3         ; 82C461 Chip ID and Revision (ro)
  72. ;**************************************************************
  73. BIT=7654        ; 82C461 Chip ID
  74.                 0000= SL82C461
  75. BIT=3210        ; 82C461 Chip Revision
  76. ;**************************************************************
  77. INDEX=4         ; 82C362 Chip ID and Revision (ro)
  78. ;**************************************************************
  79. BIT=7654        ; 82C362 Chip ID
  80.                 0001= SL82C362
  81. BIT=3210        ; 82C362 Chip Revision
  82. ;**************************************************************
  83. INDEX=5         ; DMA Command Control
  84. ;**************************************************************
  85. BIT=76          ; DMA Read command delay
  86.                 00= 0 cycles (default)
  87.                 01= 1 cycle
  88.                 10= 2 cycles
  89.                 11= 3 cycles
  90. BIT=54         ; DMA cycle Wait states
  91.                 00= 0 Waitstates
  92.                 01= 1 Waitstate (default)
  93.                 10= 2 Waitstates
  94.                 11= 3 Waitstates
  95. BIT=3210        ; Reserved
  96. ;**************************************************************
  97. INDEX=6         ; Miscellaneous Control
  98. ;**************************************************************
  99. BIT=7           ; must be 0
  100. BIT=6543        ; reserved
  101. BIT=2           ;0/1 decoupled refresh
  102. BIT=1           ;0/1 cache posted write buffer
  103. BIT=0           ; reserved
  104. ;**************************************************************
  105. INDEX=7         ; Parity Check enable
  106. ;**************************************************************
  107. BIT=76543       ;reserved
  108. BIT=2           ;1/0 memory parity check
  109. BIT=1           ;reserved
  110. BIT=0           ;must be 0
  111. ;**************************************************************
  112. INDEX=8         ; AT Bus Cycle Command Control
  113. ;**************************************************************
  114. BIT=7           ;command delay
  115.                 0= 0 Cycles for Mem 16 Bit, else 1 Cycle
  116.                 1= 2 Cycles for Mem 16 Bit, else 3 Cycles
  117. BIT=6           ;16-bit AT Bus  cycle waitstate
  118.                 0= 1 Waitstate
  119.                 1= 3 Waitstates
  120. BIT=5           ;8-bit AT Bus cycle waitstate
  121.                 0= 3 Waitstate
  122.                 1= 5 Waitstates
  123. BIT=4           ;On Chipset I/O Waitstate
  124.                 0= 2 Waitstate
  125.                 1= 4 Waitstates
  126. BIT=32          ;I/O recovery time
  127.                 00= 0 Sysclk
  128.                 01= 4 Sysclk
  129.                 10= 8 Sysclk
  130.                 11=12 Sysclk
  131. BIT=1           ;0/1 Extended ALE
  132. BIT=0           ;0/1 Extended Ready# (ro)
  133. ;**************************************************************
  134. INDEX=20H       ; DRAM Configuration Bank 0/1
  135. ;**************************************************************
  136. BIT=76          ;Bank 0 DRAM Typ
  137.                 00= disabled
  138.                 01= 256KBit (default)
  139.                 10= 1MBit
  140.                 11= 4MBit
  141. BIT=5           ;0/1 Page Mode
  142. BIT=43          ;Bank 1 DRAM Typ
  143.                 00= disabled
  144.                 01= 256KBit (default)
  145.                 10= 1MBit
  146.                 11= 4MBit
  147. BIT=210         ;reserved
  148. ;**************************************************************
  149. INDEX=21H       ; DRAM Configuration Bank 2/3
  150. ;**************************************************************
  151. BIT=76          ;Bank 2/3 DRAM Typ
  152.                 00= disabled
  153.                 01= 256KBit (default)
  154.                 10= 1MBit
  155.                 11= 4MBit
  156. BIT=5           ;reserved
  157. BIT=4          ;Bank 2/3 Number of banks used
  158.                 0= no or 1 bank (default)
  159.                 1= 2 banks
  160. BIT=3210       ;reserved
  161. ;**************************************************************
  162. INDEX=22H      ; Bank 0 Ending Address
  163. BIT=76543210   ; A26..A19
  164. INDEX=23H      ; Bank 1 Ending Address
  165. BIT=76543210   ; A26..A19
  166. INDEX=24H      ; Bank 2 Ending Address
  167. BIT=76543210   ; A26..A19
  168. INDEX=25H      ; Bank 3 Ending Address
  169. BIT=76543210   ; A26..A19
  170. ;**************************************************************
  171. INDEX=26H      ; Refresh period
  172. ;**************************************************************
  173. BIT=76         ; reserved
  174. BIT=54         ; Refresh period
  175.                00= 15 
  176. s (default)
  177.                01= 30 
  178.                10= 60 
  179.                11= 120 
  180. BIT=3210       ; reserved
  181. ;**************************************************************
  182. INDEX=27H      ; /RAS Timeout
  183. ;**************************************************************
  184. BIT=76         ;/RAS Timeout period:
  185.                00=10
  186. s (default)
  187.                01=20
  188.                10=40
  189.                11=80
  190. BIT=543210     ;reserved
  191. ;**************************************************************
  192. INDEX=28H      ; x36SIMM-Support
  193. ;**************************************************************
  194. BIT=765        ;reserved
  195. BIT=4          ;DRAM/SIMM type
  196.                0=9 bit DRAM/SIMM installed
  197.                1=x36 SIMM installed
  198. BIT=3          ;x36 SIMM Socket 3 density
  199.          0=Single Density, RAS of odd Bank on socket 3 is enabled
  200.          1=Double Density, RAS of both Banks on socket 3 are enabled
  201. BIT=2          ;x36 SIMM Socket 2 density
  202.          0=Single Density, RAS of odd Bank on socket 2 is enabled
  203.          1=Double Density, RAS of both Banks on socket 2 are enabled
  204. BIT=1          ;x36 SIMM Socket 1 density
  205.          0=Single Density, RAS of odd Bank on socket 1 is enabled
  206.          1=Double Density, RAS of both Banks on socket 1 are enabled
  207. BIT=0          ;x36 SIMM Socket 0 density
  208.          0=Single Density, RAS of odd Bank on socket 0 is enabled
  209.          1=Double Density, RAS of both Banks on socket 0 are enabled
  210. ;**************************************************************
  211. INDEX=2DH      ; Memory Relocation/combined BIOS
  212. ;**************************************************************
  213. BIT=76         ;Relocation:
  214.                00= disabled
  215.                01= illegal
  216.                10= 256 KB
  217.                11= 384 KB
  218. BIT=5          ;0/1 Extended Combined BIOS
  219. BIT=4          ;0/1 Extended Combined BIOS region E8000h-EFFFFh:
  220. BIT=3          ;0/1 Extended Combined BIOS region E0000h-E7FFFh:
  221. BIT=2          ;0/1 Extended Combined BIOS region C8000h-CFFFFh:
  222. BIT=1          ;0/1 Extended Combined BIOS region C0000h-C7FFFh:
  223. BIT=0          ;reserved
  224. ;**************************************************************
  225. INDEX=2EH      ; Shadow RAM Enable 1
  226. ;**************************************************************
  227. BIT=76         ;Shadow CC000h-CFFFFh:
  228.                00= Read from ROM/ATBUS, RAM disable
  229.                01= Read from ROM/ATBUS, Write to RAM
  230.                10= Read from RAM, Write protected
  231.                11= Read from RAM, Write to RAM
  232. BIT=54         ;Shadow C8000h-CBFFFh:
  233.                00= Read from ROM/ATBUS, RAM disable
  234.                01= Read from ROM/ATBUS, Write to RAM
  235.                10= Read from RAM, Write protected
  236.                11= Read from RAM, Write to RAM
  237. BIT=32         ;Shadow C4000h-C7FFFh:
  238.                00= Read from ROM/ATBUS, RAM disable
  239.                01= Read from ROM/ATBUS, Write to RAM
  240.                10= Read from RAM, Write protected
  241.                11= Read from RAM, Write to RAM
  242. BIT=10         ;Shadow C0000h-C3FFFh:
  243.                00= Read from ROM/ATBUS, RAM disable
  244.                01= Read from ROM/ATBUS, Write to RAM
  245.                10= Read from RAM, Write protected
  246.                11= Read from RAM, Write to RAM
  247. ;**************************************************************
  248. INDEX=2FH      ; Shadow RAM Enable 2
  249. ;**************************************************************
  250. BIT=76         ;Shadow DC000h-DFFFFh:
  251.                00= Read from ROM/ATBUS, RAM disable
  252.                01= Read from ROM/ATBUS, Write to RAM
  253.                10= Read from RAM, Write protected
  254.                11= Read from RAM, Write to RAM
  255. BIT=54         ;Shadow D8000h-DBFFFh:
  256.                00= Read from ROM/ATBUS, RAM disable
  257.                01= Read from ROM/ATBUS, Write to RAM
  258.                10= Read from RAM, Write protected
  259.                11= Read from RAM, Write to RAM
  260. BIT=32         ;Shadow D4000h-D7FFFh:
  261.                00= Read from ROM/ATBUS, RAM disable
  262.                01= Read from ROM/ATBUS, Write to RAM
  263.                10= Read from RAM, Write protected
  264.                11= Read from RAM, Write to RAM
  265. BIT=10         ;Shadow D0000h-D3FFFh:
  266.                00= Read from ROM/ATBUS, RAM disable
  267.                01= Read from ROM/ATBUS, Write to RAM
  268.                10= Read from RAM, Write protected
  269.                11= Read from RAM, Write to RAM
  270. ;**************************************************************
  271. INDEX=30H      ; Shadow RAM Enable 3
  272. ;**************************************************************
  273. BIT=76         ;Shadow E0000h-EFFFFh:
  274.                00= Read from ROM/ATBUS, RAM disable
  275.                01= Read from ROM/ATBUS, Write to RAM
  276.                10= Read from RAM, Write protected
  277.                11= Read from RAM, Write to RAM
  278. BIT=543210     ;reserved
  279. ;**************************************************************
  280. INDEX=31H      ; Shadow RAM Enable 4/ Flash EPROM Support
  281. ;**************************************************************
  282. BIT=76         ;Shadow F0000h-FFFFFh:
  283.                00= Read from ROM, RAM disable
  284.                01= Read from ROM, Write to RAM
  285.                10= Read from RAM, Write protected
  286.                11= Read from RAM, Write to RAM
  287. BIT=543        ;reserved
  288. BIT=2          ; Pin 13 definition for non-cache system:
  289.                0= /NPRDY
  290.                1= /LDEV
  291. BIT=1          ;Flash EPROM Support
  292.                0= Read Only EPROM
  293.                1=R/W EPROM
  294. BIT=0          ;0/1 Inverted SA16 during ROM access cycle
  295. ;**************************************************************
  296. INDEX=32H      ; DRAM Timing 1
  297. ;**************************************************************
  298. BIT=76         ; /CAS Pulse width (depends on Reg 33, Bit 0)
  299.                00=reserved (33_0=0) / 5 CClK2 (33_0=1)
  300.                01=2 CCLK2  (33_0=0) / 6 CCLK2 (33_0=1)
  301.                10=3 CCLK2  (33_0=0) / reserved(33_0=1)
  302.                11=4 CCLK2  (33_0=0) / reserved(33_0=1)
  303. BIT=543       ;/RAS Precharge
  304.               000= reserved
  305.               001= 2 CCLK2 Cycles
  306.               010= 3 CCLK2 Cycles
  307.               011= 4 CCLK2 Cycles
  308.               100= 5 CCLK2 Cycles
  309.               101= reserved
  310.               11x= reserved
  311. BIT=210       ;/RAS Pulse width
  312.               000= reserved
  313.               001= reserved
  314.               010= 3 CCLK2 Cycles
  315.               011= 4 CCLK2 Cycles
  316.               100= 5 CCLK2 Cycles
  317.               101= 6 CCLK2 Cycles
  318.               11x= reserved
  319. ;**************************************************************
  320. INDEX=33H      ; DRAM Timing 2
  321. ;**************************************************************
  322. BIT=76        ;/RAS to column address
  323.               00=0.5 CCLK2 Cycle
  324.               01=1   CCLK2 Cycle
  325.               10=1.5 CCLK2 Cycle
  326.               11=2   CCLK2 Cycle
  327. BIT=54        ;/RAS to /CAS
  328.               00=1 CCLK2 Cycle
  329.               01=2 CCLK2 Cycle
  330.               10=3 CCLK2 Cycle
  331.               11=4 CCLK2 Cycle
  332. BIT=3         ; CAS Precharge
  333.               0= 1 CCLK2 Cycle
  334.               1= 2 CCLK2 Cycle
  335. BIT=21        ;reserved
  336. BIT=0         ;/CAS Pulse width (together with reg 32, Bit=76)
  337. ;**************************************************************
  338. INDEX=40H      ; SL82C465 Cache Controller
  339. ;**************************************************************
  340. ;**************************************************************
  341. INDEX=40H      ; Burst & Flush
  342. ;**************************************************************
  343. BIT=76         ; Burst Transfer:
  344.                00= disabled
  345.                01= 2 Cycle Burst
  346.                10= 4 Cycle Burst
  347.                11= reserved
  348. BIT=54210      ; must be 0
  349. BIT=3          ;0/1 Flush control
  350. ;**************************************************************
  351. INDEX=43H      ; Non Cacheable Region 2 High Base Address
  352. ;**************************************************************
  353. BIT=76543210   ; A25..A18
  354. ;**************************************************************
  355. INDEX=44H      ; Non Cacheable Region 2 Low Base Address
  356. ;**************************************************************
  357. BIT=76         ; A17..A16
  358. BIT=543        ; Size
  359.                000= disabled
  360.                001= 64K
  361.                010=128K
  362.                011=256K
  363.                100=512K
  364.                101=1M
  365.                110=2M
  366.                111=4M
  367. ;**************************************************************
  368. INDEX=45H      ; Non Cacheable Region 3
  369. ;**************************************************************
  370. BIT=7          ; Turbo/Compatible Speed Control
  371.                0= Turbo
  372.                1= Compatible
  373. BIT=6          ;reserved
  374. BIT=5          ;0/1 F0000h-FFFFFh Cacheable (only if Shadow RAM)
  375. BIT=4          ;0/1 C8000h-CFFFFh Cacheable (only if Shadow RAM)
  376. BIT=3          ;0/1 C0000h-C7FFFh Cacheable (only if Shadow RAM)
  377. BIT=210        ;maximal cacheable Address:
  378.                000= disabled
  379.                011= 32MB
  380.                010= 16MB
  381.                001=  8MB
  382.                101=  4MB
  383.                100=  2MB
  384.                111=  1MB
  385.                110=  512 KB
  386. ;**************************************************************
  387. ; Cache-Konfiguration
  388. ;**************************************************************
  389. ; Ist nicht softwarem
  390. ig konfigurierbar, wird bei Power-On
  391. ; durch Pegel an bestimmten Pins des SL82C465 festgelegt:
  392. ; 1= offen, 0= 4k7 Pull-Down
  393. ; PIN=60      ;Clock Mode
  394. ;             0= 1X clock mode (bis 50/50 MHz)
  395. ;             1= 2X clock mode (bis 33/66 MHz)
  396. ; PIN=37,31   ;Cache line size
  397. ;             00= 1 Dword
  398. ;             01= 2 Dwords
  399. ;             10= 4 Dwords
  400. ;             11= 1 Dword
  401. ;PIN=76       ; SRAM banks
  402. ;             0= 1 bank or 4 banks
  403. ;             1= 1 bank or 2 banks
  404. ;PIN=48      ; Burst fill rate
  405. ;            0=3-2-2-2-Burst
  406. ;            1=2-1-1-1-Burst
  407. ;PIN=49      ; Write wait state
  408. ;            0= 0 Wait states
  409. ;            1= 1 Wait states
  410. ;PIN=52     ; Combined Valid/tag SRAM
  411. ;            0= not combined
  412. ;            1= combined
  413. ;**************************************************************
  414. ; Hardware-Konfiguration
  415. ;**************************************************************
  416. ; Ist nicht softwarem
  417. ig konfigurierbar, wird bei Power-On
  418. ; durch Pegel an bestimmten Daten-Pins des SL82C461 festgelegt:
  419. ; 1= offen, 0= 4k7 Pull-Down
  420. ;PIN=24,23  ; CPU-Type (XD1,XD0)
  421. ;              00= reserved
  422. ;              01= 486
  423. ;              10= 386SX
  424. ;              11= 386DX
  425. ;PIN=25     ;1/0 Extended Ready (XD2)
  426. ;PIN=26     ;EPROM Data Width (XD3)
  427. ;            0= 8 Bit
  428. ;            1=16Bit
  429. ;PIN=31     ;EPROM Wait State (XD4)
  430. ;           0= 1 Wait state
  431. ;           1= 3 Wait states
  432. ;PIN=35     ;1/0 Combined BIOS (XD5)
  433. ;PIN=37     ;1/0 Cache system  (XD6)
  434.