Magazyn Enter 1999 January/enter_01_1999_2.iso/BIOS/ctchip34/SIS471.CFG

Text File | 1994-11-07 | 24KB | 700 lines

;********************************************************************
NAME=SiS471 ;SiS85C471 Single Chip in Datei SiS471.CFG
;********************************************************************

INDEXPORT=22h
DATENPORT=23h

;######  Macros  Aufruf  ctchipz  /xxxx [/L]  #####
;######  Macros 1.Buchstabe keine Ziffer! #####

MACRO= FASTEST = 50h:111xxxxx, 51h:xxxxxx10, 58h:x11xxxxx
MACRO= FASTER  = 50h:101xxxxx, 51h:xxxxxx10, 58h:x11xxxxx
MACRO= SLOWER  = 50h:010xxxxx, 51h:xxxxxx01, 58h:x01xxxxx
MACRO= SLOWEST = 50h:000xxxxx, 51h:xxxxxx01, 58h:x00xxxxx

MACRO= L2ON    = FLUSH, 51h:1xxxx0xx, FLUSH, 51h:1xxxx1xx
MACRO= L2OFF   = FLUSH, 51h:0xxxx1xx

MACRO= L2WB    = L2OFF, 50h:xxxx1xxx, L2ON
MACRO= L2WT    = L2OFF, 50h:xxxx0xxx, L2ON
MACRO= ALLDIRTY= L2OFF, 72h:xxxxx10x, L2ON
MACRO= DIRTY   = L2OFF, 72h:xxxxx11x, L2ON
MACRO= EXTDIRTY= L2OFF, 72h:xxxxx01x, L2ON ;


;********************************************************************
INDEX=50h;  Memory Configuration
;********************************************************************
BIT=7   ; Cache-Read Leading Cycle (if Reg5A Bit 7=0)
         0 = 3 Takte
         1 = 2 Takte

BIT=76  ;DRAM Speed
           00=Slowest   (50MHz 4-3-4, CAS Puls= 2T)
           01=Slower    (40MHz 4-3-3  CAS Puls= 1T)
           10=Faster    (33MHz 3-2-2  CAS Puls= 2T)
           11=Fastest   (25MHz 3-2-2  CAS Puls= 1T)


BIT=5   ;DRAM Write CAS Pulse Width
           0=2T
           1=1T

BIT=4  ;L1-Write Strategy
           0 = WT
           1 = WB

BIT=3  ;L2-Write Strategy
           0 = WT
           1 = WB

BIT=2  ; PIN 138 Mulitiplex Output Control
           0 = PIN 138 = RAS  ( > 2 RAM Banks)
           1 = PIN 138 = MA11 ( 16 M SIMM DRAMs)

BIT=1  ;0/1 L1-Burst Write (only if Bit4 is set)

BIT=0  ;Reset (INIT active enable)
           0 = Normal Reset
           1 = Warm Reset

;********************************************************************
INDEX=51h ; Cache Konfiguration
;********************************************************************
BIT=7   ;0/1 L2-Cache Enable

BIT=654  ;Cache Size
           000= 32KB
           001= 64KB
           010=128KB
           011=256KB
           100=512KB
           101=  1M

BIT=3   ;0/1 Cache Interleave Enable

BIT=2   ; Cache On/Off
           0 = Off
           1 = On


BIT=1   ;Cache Write Cycle
           0=3T (Single)
           1=2T (Single)

           0=2T (Write-Burst)
           1=1T (Write-Burst)

BIT=0   ;Cache Burst Read Cycle
           0=1T
           1=2T

;********************************************************************
INDEX=52h; Shadow
;********************************************************************
BIT=7   ;0/1 Shadow RAM Read Enable

BIT=6   ;0/1 Shadow RAM Write Protection Enable

BIT=5   ;0/1 E8000h-EFFFFh Shadow RAM Enable
BIT=4   ;0/1 E0000h-E7FFFh Shadow RAM Enable
BIT=3   ;0/1 D8000h-DFFFFh Shadow RAM Enable
BIT=2   ;0/1 D0000h-D7FFFh Shadow RAM Enable
BIT=1   ;0/1 C8000h-CFFFFh Shadow RAM Enable
BIT=0   ;0/1 C0000h-C7FFFh Shadow RAM Enable

;********************************************************************
INDEX=53h; Shadow
;********************************************************************
BIT=7   ;System BIOS ROM Size
           0= 64K
           1=128K

BIT=6   ;0/1 Combine System  BIOS with C0000h-C7FFFFh Region

BIT=5   ;0/1 F0000h-FFFFFh Shadow RAM Cacheable

BIT=4   ;0/1 C0000h-C7FFFh Shadow RAM Cacheable

BIT=321 ;A26 .. A24 for DMA Cycle Up to 64 MB

BIT=0   ;0/1 Data Parity Check

;********************************************************************
INDEX=54h; Non cacheable 1
;********************************************************************
BIT=7   ;Allocation of Non-cacheable Area #1
           0=Local DRAM
           1=AT Bus, local DRAM is disabled

BIT=654 ;Size of Non-cacheable Area #1 (within 16 MB)
           000=  0KB (disabled)
           001= 64KB
           010=128KB
           011=256KB
           100=512KB
           101=  1MB
           110=  2MB
           111=  4MB

BIT=3   ;Allocation of Non-Cacheable Area #2
           0=Local DRAM
           1=AT Bus, local DRAM is disabled

BIT=210 ;Size of Non-Cacheable Area #2 (within 64 MB)
           000=  0KB (disabled)
           001= 64KB
           010=128KB
           011=256KB
           100=512KB
           101=  1MB
           110=  2MB
           111=  4MB

;********************************************************************
INDEX=55h; Non Cacheable 1 A23..A16
;********************************************************************
BIT=76543210    ;A23-A16 of Non-Cacheable Area #1 (within 16 MB)

;********************************************************************
INDEX=56h; Non Cacheable 2 A23..A16
;********************************************************************
BIT=76543210    ;A23-A16 of Non-Cacheable Area #2 (within 128 MB)

;********************************************************************
INDEX=57h;
;********************************************************************
BIT=76  ;A25 and A24 of Non-Cacheable Area #2

BIT=5   ;0/1 GATE A20 Emulation

BIT=4   ;0/1 Fast Reset Emulation

BIT=3   ;Fast Reset Latency Control
           0=2 µs
           1=6 µs

BIT=2   ;Slow Refresh Enabled (1:4)
           0=Normal Refresh
           1=Slow Refresh

BIT=1   ;0/1 Gate A20 Emulation Mode

BIT=0   ;Cache Sizing Enable
           0=Normal Operation
           1=Always Cache Hit

;********************************************************************
INDEX=58h;
;********************************************************************
BIT=7   ;0/1 Slow CPU (below 25MHz)

BIT=6   ;DRAM Writestate
           0=1 Waitstate
           1=0 Waitstate

BIT=5   ;Refresh Cycle Hold CPU
           0= Enable (Standard Refresh)
           1= Disable (Hidden Refresh)

Bit=4   ;De Turbo Hold Time
           0= 4 µs (every 12 µs)
           1= 8 µs (every 12 µs)

Bit=3   ;Reserved (=1)

Bit=2   ;0/1 Combine System BIOS with C8000h-CFFFFh

Bit=1   ;Local Bus RDY
           0=2T
           1=3T

Bit=0   ;SElect Local Bus Ready
           0=Synchonized by clock (Synchronous mode)
           1=directly passed through the output buffer (Tranparent Mode)

;********************************************************************
INDEX=59h;  Local Bus Support
;********************************************************************

BIT=7   ;De-Turbo On/Off
           0= Turbo
           1= De-Turbo

BIT=6   ; De-Turbo Switch Enable
           0= De-Turbo switch enabled
           1= Always Turbo

BIT=543210 ; DRAM Size Configuration

;********************************************************************
INDEX=5Ah;
;********************************************************************

BIT=7   ; Reserved =0
BIT=6   ; Overwrite the Cache Read Cycle Time (Bit7 of reg 50h)
           0= Keep the access time that defined in the Register 50 Bit 7
           1= Force all the first Cycle Time of Cache access to be 2T

Bit=5   ; Reserved = 0

Bit=4   ; Reading the De-Turbo Status (Read Only)
            0=Turbo
            1=De-Turbo
Bit=32  ; Reserved =0
Bit=1   ; Cyrix M7 CPU L1 Cache Burst Write Timing Control
;         This bit is only valid when M7 CPU is used
           0= Always support 3-2-2-2,
;         regardless register 51 bit 1 and register 50 Bit bit 7
           1= Be able to support 2-1-1-1

BIT=0  ;0/1  Local Master Access DRAM Cycle CASn Delay 1T

;********************************************************************
INDEX=5Bh;  SMM
;********************************************************************

BIT=7    ;0/1 SMM (via SMI Or IRQ12/15)
BIT=6    ;0/1 Stop Clock
;        When enabled a sequence of reading I/O-port 43h followed by
;        reading I/O-port 070h forces SiS85C471 to assert STPCLK

BIT=5    ;0/1 STPCLK Auto Generation Select
;        When enabled the SiS85C471 asserts STPCLK when system times
;        expires, break switch is pressed or software SMI port is accessed

BIT=4    ; System Management Mode Request Selection
           0= By IRQ
           1= By SMI
;        Alternative Way to enter system management mode by using IRQn
;        for CPUs without SMI input pin. Note that when bit 5 of
;        Register 5B is set to 1 this bit should be set to 1

BIT=3    ; IRQ-Channel Selection (only if Register 5B Bit 4 = 0)
           0= Select IRQ12
           1= Select IRQ15

BIT=2    ;0/1 SYSCLK Frequency Auto-Switch
;        During CPU Clock Scaling, SYSCLK will be changed to 7.159 MHz.
;        Once CPU Clock is resumed to the normal state, the SYSCLK will
;        return to the frequency

BIT=1    ;1/0 Relocate Enable
BIT=0    ; Reserved

;********************************************************************
INDEX=5Ch;  Interrupt Vector Adress Trap Mask 1
;********************************************************************
BIT=76543210 ;

;********************************************************************
INDEX=5Dh;  Interrupt Vector Adress Trap Mask 2
;********************************************************************
BIT=76543210 ;

;********************************************************************
INDEX=5Eh;  Interrupt Vector Adress Trap Mask 3
;********************************************************************
BIT=76543210 ;

;********************************************************************
INDEX=5Fh;
;********************************************************************
BIT=76543210 ;

;********************************************************************
INDEX=60h;  Bus Takt
;********************************************************************

BIT=765 ; Bus Clock Frequency
           000= BUSCLK = 7.159 MHz
           001= BUSCLK = 1/10 CLKIN
           010= BUSCLK = 1/8  CLKIN
           011= BUSCLK = 1/6  CLKIN
           100= BUSCLK = 1/5  CLKIN
           101= BUSCLK = 1/4  CLKIN
           110= BUSCLK = 1/3  CLKIN
           111= BUSCLK = 1/2  CLKIN

BIT=4    ;0/1 Zero Wait for 16-Bit Memory or I/O Command
BIT=3    ;0/1 Command Delay for 16-Bit I/O Read
BIT=2    ;0/1 Decrease 16-Bit I/O Read Cycle 1 AT Bus Clock
BIT=10   ;Reserved

;********************************************************************
INDEX=61h;  Bus -I/O-Recovery, -Waits
;********************************************************************

BIT=76  ; 16-Bit-I/O-Recovery
           00= 8 BUSCLK
           01= 5 BUSCLK
           10= 3 BUSCLK
           11= 2 BUSCLK

BIT=54  ; 8-Bit-I/O-Recovery
           00= 16 BUSCLK
           01= 11 BUSCLK
           10=  7 BUSCLK
           11=  4 BUSCLK

BIT=3   ; Reserved (1)

BIT=2   ; 16-Bit Memory I/O Waitstate
           0=2 Waitstate
           1=1 Waitstate

BIT=1   ; 8-Bit Memory I/O Waitstate
           0=5 Waitstate
           1=4 Waitstate

BIT=0   ; Reserved (1)

;********************************************************************
INDEX=62h;  Reserved
;********************************************************************

BIT=7     ; Reserved

BIT=6     ; Reserved and should be written with 1

BIT=543210; Reserved

;********************************************************************
INDEX=63h ; SM-RAM, Wake-up from Stop Clock/Clock Scaling/Clock Throttling
;********************************************************************

BIT=765   ; SM-RAM Area select
           000= Remap E segment to A segment
           001= Remap E segment to B segment
           010= E segment

BIT=4   ; SM-RAM Access control
           0= SM-RAM can be accessed only through SMM
           0=        (SMIACT* is active low)
           1= SM-RAM can be accessed during normal operation

BIT=3   ;0/1 Wake up by IRQn

BIT=2   ;0/1 Wake up by NMI

BIT=1   ;0/1 Wake up by DMA

BIT=0   ;0/1 Wake up by Local Master request

;********************************************************************
INDEX=64h   ;Define Software_SMI low byte address A7-A0
;********************************************************************

BIT=76543210 ; This register defines the lower 8 bits of SW_SMI
;              address trap address. bit[7:0] correspond to address
;              A[7:0]. If SW_SMI is enabled (defined in register 68,
;              bit 1) an I/O write to the address defined in
;              Registers 64 and 65 will force th SiS85C471 to generate
;              software SMI*. Software SMI* can be used to support APM.

;********************************************************************
INDEX=65h   ;Define Software_SMI high byte address A15-A8
;********************************************************************
BIT=76543210 ;

;********************************************************************
INDEX=66h   ; System event timer is reloaded by IRQ0-7 or
;              Stop Clock Break selects Register 1.
;********************************************************************

BIT=7   ;1/0 IRQ7
BIT=6   ;1/0 IRQ6
BIT=5   ;1/0 IRQ5
BIT=4   ;1/0 IRQ4
BIT=3   ;1/0 IRQ3
BIT=2   ;1/0 IRQ2
BIT=1   ;1/0 IRQ1
BIT=0   ;1/0 IRQ0

;********************************************************************
INDEX=67h   ; System event timer is reloaded by IRQ8-15
;              or Stop Clock Break selects Register 2.
;********************************************************************
;    0: IRQn active will force STPLK* to go high, if Reg 63 bit 3
;       is enabled.
;    1: IRQn active will not influence STPCLK*.

BIT=7   ;1/0 IRQ15
BIT=6   ;1/0 IRQ14
BIT=5   ;1/0 IRQ13
BIT=4   ;1/0 IRQ12
BIT=3   ;1/0 IRQ11
BIT=2   ;1/0 IRQ10
BIT=1   ;1/0 IRQ09
BIT=0   ;1/0 IRQ08

;********************************************************************
INDEX=68h; SMI/IRQ enable register
;********************************************************************

BIT=7   ;0/1 I/O Device Standby timer time out control

BIT=6   ;0/1 Programmable I/O Device Standby exit control

BIT=5   ;0/1 Serial or Parallel Port Standby exit control

BIT=4   ;0/1 Hard Disk standby exit control

BIT=3   ;0/1 Screen save mode exit control

BIT=2   ;0/1 Break switch SMI/IRQ control

BIT=1   ;0/1 Software SMI/IRQ control

BIT=0   ;0/1 System event timer time out SMI/IRQ control

;********************************************************************
INDEX=69h; SMI/IRQ request status register: (read Only!)
;********************************************************************

BIT=7   ; I/O device standby timer time out request

BIT=6   ; Programmable I/O device standby exit request

BIT=5   ; Serial port or parallel port standby exit request
;         (refer to bit 0 and 1 of the register 73 for the port selected)

BIT=4   ; Hard disk standby exit request

BIT=3   ; Local Standby/Clock Scaling/Clock Throttling exit request

BIT=2   ; Break switch SMI/IRQ request
;         If the SMM was enabled and Register 68 bit 2 = "1" and
;         Register 71 bit 7 = "0", then this bit can be set by
;         writing an "1". If the Register 71 bit 7 = "1", then
;         this bit can be set by the RC or the De-Turbo pin.

BIT=1   ; Software SMI/IRQ request
;         This bit can be set by enabling the Register 68 bit 1 and
;         an I/O write to the address defined in the registerpair 64/65.

BIT=0   ; System event timer time out SMI/IRQ Request
          0= not requested
          1= requested

;         If the SMM is enabled and the register 5B bit 5 is set to
;         0 (disable) and the Register 68 bit 0 is set to 1 (enable),
;         then this bit can be set to 1 when a time out of the system
;         timer happens.
;         Which of the SMI/IRQ functions should be serviced could be
;         decided by the SMI handler while reading this register.

;********************************************************************
INDEX=6A
;********************************************************************

BIT=76543210   ; SMOUT 7-0

;********************************************************************
INDEX=6B; SMI_CLR Register
;********************************************************************

;        When a SMI or IRQ 12/15 is active, 85C471 will not allow
;        a new SMI or IRQ 12/15 generated until this register is
;        wrote, CPU state have been restored, and a 6 us timer
;        times out.

;********************************************************************
INDEX=6C; SMI_MASK Register/Port 70h Shadow Register
;********************************************************************

;        Read from or write to this register has different meaning.
;        When read this register, the index value written to port 70h
;        ist got. When a SMI or IRQ 12/15 is active, 85C471 masks
;        out CPU resets except those resets caused by shutdown cycle
;        or hardware reset until this register is written,
;        CPU state has been restored, and a 14 us timer times out.

;********************************************************************
INDEX=6D; System Event Timer Low Byte
;********************************************************************
BIT=76543210

;********************************************************************
INDEX=6E; System Event Timer High Byte
;********************************************************************
BIT=76543210
;         Each count represents 9.374 seconds. Maximum time
;         count is 614325.08 seconds. If SMM and bit 0 of
;         Register 68 are enabled, the system event timer starts
;         counting down. When the timer counts down to 0, either
;         NMI, IRQ12 or IRQ15 will be used as the system management
;         request signal if bit 5 of register 5B is disabled.
;         Time out period = (number of counts - 1)* Time Base

;********************************************************************
INDEX=6F; System timer reload event detection
;********************************************************************

BIT=7   ; 0/1 Local device detection control

BIT=6   ; 0/1 IRQn detection control
;         If this bit is enabled, any IRQ that goes active except
;         disabled by Register 66 and will relaod system event timer.

BIT=5   ; 0/1 0A0000-0BFFFF address trap detection control

BIT=4   ; 0/1 0C0000-0C7FFF address trap detection control

BIT=3   ; 0/1 0..3FF INT vector address trap detect control

BIT=2   ; 0/1 DMA request detection control

BIT=1   ; 0/1 Local master request detection control

BIT=0   ; 0/1 Programmable I/O Port address register
;         (please refer to Registers 70 and 71)

;********************************************************************
INDEX=70h; Programmable I/O port address register
;********************************************************************

BIT=76543210 ; A9-A2

;********************************************************************
INDEX=71h
;********************************************************************

BIT=76   ; Break switch pin select
          0X: Disabled
          10: the RC pin is used as the break switch pin
          11: the De-Turbo pin is used as the break switch pin

BIT=5   ; Pin 58 definition
           0: as SMOUT1
           1: as SMOUTWL*

BIT=432   ; Programmable I/O port address mark
         000: no mask
         001: mask A0
         010: msk A1-A0
         011: mask A2-A0
         100: mask A3-A0
         101: mask A4-A0
         100: mask A5-A0
         111: mask A6-A0
;        When Programmable I/O port detection control bit in the
;        register 6F bit 0 is enabled, an I/O access
;        to the address defined in the Registers 70 and 71 will
;        force the system event timer to be reloaded.

BIT=10   xx= Programmable I/O port address A1, A0
;        When I/O trap address enabled bit, bit 0 of Register 6F,
;        is enabled, I/O command accessing the
;        address is defined by registers 70 and 71 will force
;        System event timer to be reloaded.

;********************************************************************
INDEX=72h ; CPUCLK, RAS & Dirty
;********************************************************************

BIT=7   ; 0/1 Clock throttling
;         When STPCLK* is active and this bit is enabled, a coming
;         IRQ0 will force the STPCLK* to go inactive until an EOI
;         command for the IRQ0 is issued.

BIT=6   ; 0/1 CPUCLK scaling controlled by SMOUT

BIT=5   ; CPUCLK scaling control select
         000= by SMOUT0
         001= by SMOUT1
         010= by SMOUT2
         011= by SMOUT3
         100= by SMOUT4
         101= by SMOUT5
         110= by SMOUT6
         111= by SMOUT7

BIT=21   ; Dirty or RAS6,7 | SMOUT2,3 or RAS4,5
         00=\ pin 116 = SMOUT2
         00=\ pin 133 = ALT
         00=\ pin 134 = ALTWL*
         00=\ pin 137 = SMOUT3
         01=\ pin 116 = RAS4*
         01=\ pin 133 = ALT
         01=\ pin 134 = ALTWL*
         01=\ pin 137 = RAS5*
         1X=\ pin 116 = RAS4*
         1X=\ pin 133 = RAS6*
         1X=\ pin 134 = RAS7*
         1X=\ pin 137 = RAS5*
         10=\ no Alter bit (always dirty) if Write Back Mode
         11=\ combine 7 tag bits + Alter bit in one SRAM (WB)

BIT=0   ; 0/1 Port 92h support
;         This bit enables/disables the function of bit 0 and 1 of
;         port 92h. Bit 1 of port 92h is ORed with Fast_A20_Gate
;         internally to generate A20M*. If both this bit and
;         Fast_A20_Gate are 0, A20M* is a low state. Bit 0 of
:         port 92h can be cleared by CPURESET or an I/O write
;         operation. When register 50 bit 0 is set to 1, setting
;         port 92 bit 0 to 1 from 0 by an I/O write to itself, an
;         INIT is generated after a 2 us or 6 us delay depending
;         on register 57 bit 3.

;********************************************************************
INDEX=73h   ; I/O Device standby monitor
;********************************************************************

BIT=7   ; 0/1 Programmable I/O ports (Registers 71 and 70)

BIT=6   ; 0/1 I/O Ports 1F0..7h and 3F6 detect (HD 1)

BIT=5   ; 0/1 I/O ports 2F8, 3F8, 2E8, 3F8 detect (COM1..4)

BIT=4   ; 0/1 I/O ports 278h, 378h, 3BCh  (LPT1..3)

BIT=3   ; 0/1 IRQ1, 3, 4 and IRQ12 detect - Screen save mode

BIT=2   ; Screen save mode exit request status
         0= no any IRQ 1, 3, 4 or IRQ 12 request
         1= IRQ 1, 3, 4 or IRQ12 request

BIT=1   ; 0/1 Serial Port standby exit control

BIT=0   ; 0/1 Parallel Port standby exit control

;********************************************************************
INDEX=74   ; I/O Device Standby Timer
;********************************************************************
BIT=76543210
;           The time period of each count is according to the
;           setting of register 5F bit 3,2. Maximum time period
;           is 2399.75 seconds. The minimum count is 2. The timer
;           expires when any of the selected event(s) in register
;           73 bit 7-3 has been idle for a programmed period. Please
;           refer to register 68 bit 7.
;           Time out period = (number of counts - 1)* Time Base

;********************************************************************
INDEX=75h ;misc
;********************************************************************

BIT=7   ; Reserved

BIT=6   ; 0/1 IORDY* Control
;         During clock scaling, IORDY* for DMA or ISA MAster
;         transfer is active till memory transfer complete.

BIT=54  ; Reserved

BIT=3   ; 0/1 A20ML Control
;         When CPU executes SMI handler, A20ML goes high.
;         After SMI handler is done, A20ML return to previous state.

BIT=2   ; 0/1 RAS[4:4] Active Control

BIT=1   ; MA bus and MWE buffers driving capacity control
           0= 12 mA
           1= 24 mA

BIT=0   ; 0/1 Flash Memory Write Control
;         Once this bit is set to disable, it is not able to
;         reprogrammable and any write to BIOS ROM area is void.