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Magazyn Enter 1999 January
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enter_01_1999_2.iso
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BIOS
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ctchip34
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SIS461.CFG
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1994-04-20
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9KB
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282 lines
;*************************************************************
;SiS85C461 Single Chip in Datei SiS461.CFG
;*************************************************************
INDEXPORT=22h
DATENPORT=23h
;*************************************************************
INDEX=50h; Memory Configuration
;*************************************************************
BIT=76 ;DRAM Speed
00=Slowest (50MHz)
01=Slower (40MHz)
10=Faster (33MHz)
11=Fastest (25MHz)
Bit=7 ;Bit 7 also defines the first cache read cycle time of
; a burst
0=3-x-x-x-Burst
1=2-x-x-x-Burst
BIT=5 ;DRAM Write CAS Pulse Width
0=2T
1=1T
BIT=43210 ;DRAM Size Configuration, (I)= Dword-Interleave
00000= B1:1M B2:- B3:- B4:- Total:1M
00001= B1:1M B2:1M B3:- B4:- Total:2M (I)
00010= B1:1M B2:1M B3:2M B4:- Total:4M
00011= B1:1M B2:1M B3:4M B4:- Total:6M
00100= B1:1M B2:1M B3:2M B4:4M Total:8M
00101= B1:1M B2:1M B3:4M B4:4M Total:10M (I)
00110= B1:1M B2:1M B3:16M B4:- Total:18M
00111= B1:2M B2:- B3:- B4:- Total:2M
01000= B1:2M B2:2M B3:- B4:- Total:4M (I)
01001= B1:2M B2:4M B3:- B4:- Total:6M
01010= B1:2M B2:2M B3:4M B4:- Total:8M
01011= B1:2M B2:2M B3:4M B4:4M Total:12M (I)
01100= B1:2M B2:16M B3:- B4:- Total:18M
01101= B1:2M B2:2M B3:16M B4:- Total:20M
01110= B1:2M B2:2M B3:4M B4:- Total:24M
01111= B1:2M B2:2M B3:16M B4:- Total:36M (I)
10000= B1:4M B2:- B3:- B4:- Total:4M
10001= B1:4M B2:4M B3:- B4:- Total:8M (I)
10010= B1:4M B2:4M B3:4M B4:- Total:12M
10011= B1:4M B2:4M B3:4M B4:4M Total:16M (I)
10100= B1:4M B2:16M B3:- B4:- Total:20M
10101= B1:4M B2:4M B3:16M B4:- Total:24M
10110= B1:4M B2:16M B3:16M B4:- Total:36M
10111= B1:4M B2:4M B3:16M B4:16M Total:40M (I)
11000= B1:8M B2:- B3:- B4:- Total:8M
11001= B1:8M B2:8M B3:- B4:- Total:16M (I)
11010= B1:8M B2:8M B3:8M B4:- Total:24M
11011= B1:8M B2:8M B3:8M B4:8M Total:32M (I)
11100= B1:16M B2: B3:- B4:- Total:16M
11101= B1:16M B2:16M B3:- B4:- Total:32M (I)
11110= B1:16M B2:16M B3:16M B4:- Total:48M
11111= B1:16M B2:16M B3:16M B4:16M Total:64M (I)
;*************************************************************
INDEX=51h ; Cache Konfiguration
;*************************************************************
BIT=7 ;0/1 Cache Enable
BIT=6 ;Write Back Enable
0=Disable (Write Through)
1=Enable (Write Back)
BIT=54 ;Cache Size
00= 32KB
01= 64KB
10=128KB
11=256KB
BIT=3 ;0/1 Cache Interleave Enable
BIT=2 ;0/1 DRAM Interleave Enable (for 2/4 banks only)
BIT=1 ;Cache Write Cycle
0=3T
1=2T
BIT=0 ;Cache Burst Read Cycle
0=1T
1=2T
;*************************************************************
INDEX=52h; Shadow
;*************************************************************
BIT=7 ;0/1 Shadow RAM Read Enable
BIT=6 ;0/1 Shadow RAM Write Protection Enable
BIT=5 ;0/1 E8000h-EFFFFh Shadow RAM Enable
BIT=4 ;0/1 E0000h-E7FFFh Shadow RAM Enable
BIT=3 ;0/1 D8000h-DFFFFh Shadow RAM Enable
BIT=2 ;0/1 D0000h-D7FFFh Shadow RAM Enable
BIT=1 ;0/1 C8000h-CFFFFh Shadow RAM Enable
BIT=0 ;0/1 C0000h-C7FFFh Shadow RAM Enable
;*************************************************************
INDEX=53h;
;*************************************************************
BIT=7 ;System BIOS ROM Size
0= 64K
1=128K
BIT=6 ;0/1 Combine System BIOS with C0000h-C7FFFFh Region
; for ROM area
BIT=5 ;0/1 F0000h-FFFFFh Shadow RAM Cacheable
BIT=4 ;0/1 C0000h-C7FFFh Shadow RAM Cacheable
BIT=32 ;A25 and A24 for DMA Cycle Up to 64 MB
BIT=1 ;0/1 Data Parity Check
BIT=0 ;De-Turbo Switch
0=Enable
1=Disable, ignore Status of Turbo Switch
;*************************************************************
INDEX=54h; Non cacheable 1
;*************************************************************
BIT=7 ;Allocation of Non-cacheable Area #1
0=Local DRAM
1=AT Bus, local DRAM is disabled
BIT=654 ;Size of Non-cacheable Area #1 (within 16 MB)
000= 0KB (disabled)
001= 64KB
010=128KB
011=256KB
100=512KB
101= 1MB
110= 2MB
111= 4MB
BIT=3 ;Allocation of Non-Cacheable Area #2
0=Local DRAM
1=AT Bus, local DRAM is disabled
BIT=210 ;Size of Non-Cacheable Area #2 (within 64 MB)
000= 0KB (disabled)
001= 64KB
010=128KB
011=256KB
100=512KB
101= 1MB
110= 2MB
111= 4MB
;*************************************************************
INDEX=55h; Non Cacheable 2
;**************************************************************
BIT=76543210 ;A23-A16 of Non-Cacheable Area #1 (within 16 MB)
;*************************************************************
INDEX=56h
;*************************************************************
BIT=76543210 ;A23-A16 of Non-Cacheable Area #2 (within 64 MB)
;*************************************************************
INDEX=57h
;*************************************************************
BIT=76 ;A25 and A24 of Non-Cacheable Area #2
BIT=5 ;0/1 GATE A20 Emulation
BIT=4 ;0/1 Fast Reset Emulation
BIT=3 ;Fast Reset Latency Control
0=2µs
1=6µs
BIT=2 ;Slow Refresh Enabled (1:4)
0=Normal Refresh
1=Slow Refresh
BIT=1 ;De-Turbo ON/OFF
0=Turbo
1=De-Turbo
BIT=0 ;Cache Sizing Enable
0=Normal Operation
1=Always Cache Hit
;*************************************************************
INDEX=58h;
;*************************************************************
BIT=7 ;0/1 Slow CPU (below 25MHz)
BIT=6 ;DRAM Writestate
0=1 Waitstate
1=0 Waitstate
BIT=5 ;Refresh Cycle Hold CPU
0= Enable (Standard Refresh)
1= Disable (Hidden Refresh)
Bit=4 ;De Turbo Hold Time
0= 4 µs (every 12 µs)
1= 8 µs (every 12 µs)
Bit=3 ;Reserved (=1)
Bit=2 ;0/1 Combine System BIOS with C8000h-CFFFFh for ROM area
Bit=1 ;Reserved (=0)
Bit=0 ;Overwrite the Cache Read Cycle Time
0= as defined in the bit 7 of Reg 50
1= 2T, ignore bit 7 of Reg 50
;*************************************************************
INDEX=59h; Local Bus Support
;*************************************************************
BIT=7 ;Local Bus Device Signal (LBD*) Sampling Position
0= at end of T3
1= at end of T2
BIT=6 ;CPURDY Generation Mode from LDRY
0=Synchonized by clock (Synchronous mode)
1=directly passed through the output buffer (Tranparent Mode)
BIT=4 ; De-Turbo Status (Read-Only)
0= Turbo
1= De-Turbo
BIT=53210 ; Reserved (=0)
;*************************************************************
INDEX=60h; Bus Takt
;*************************************************************
BIT=765 ; Bus Clock Frequency
000= BUSCLK = 7.159 MHz
001= BUSCLK = 1/10 CLKIN
010= BUSCLK = 1/8 CLKIN
011= BUSCLK = 1/6 CLKIN
100= BUSCLK = 1/5 CLKIN
101= BUSCLK = 1/4 CLKIN
110= BUSCLK = 1/3 CLKIN
111= BUSCLK = 1/2 CLKIN
BIT=43210; Reserved (=0)
;*************************************************************
INDEX=61h; Bus Takt
;*************************************************************
BIT=76 ; 16-Bit-I/O-Recovery
00= 8 BUSCLK
01= 5 BUSCLK
10= 3 BUSCLK
11= 2 BUSCLK
BIT=54 ; 8-Bit-I/O-Recovery
00= 16 BUSCLK
01= 11 BUSCLK
10= 7 BUSCLK
11= 4 BUSCLK
BIT=3 ; Reserved (1)
BIT=2 ; 16-Bit Memory I/O Waitstate
0=2 Waitstate
1=1 Waitstate
BIT=1 ; 8-Bit Memory I/O Waitstate
0=5 Waitstate
1=4 Waitstate
BIT=0 ; Reserved (1)