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Text File  |  1993-10-13  |  7KB  |  225 lines
  1. ;*************** OPTI 386WB: 82C391, 82C392 **********************
  2. ;*************** in Datei OPTI391.CFG       **********************
  3. INDEXPORT=22H   ;OPTI-Adressen
  4. DATENPORT=24H
  5. ;******************************************************************
  6.  
  7. INDEX=20H        ; Control-Register 1
  8. ;****************************************************************
  9. BIT=76           ; Revision  of 82C391
  10.  
  11.  
  12. BIT=3            ;0/1 Single ALE
  13.  
  14. BIT=2            ;0/1 Extra AT Cycle Waitstate
  15.  
  16. BIT=1            ;0/1 Emulation Keyboard Reset Control
  17.  
  18. BIT=0            ;0/1 Fast Reset Enable
  19.  
  20. INDEX=21H        ; Control Register 2
  21. ;****************************************************************
  22.  
  23. BIT=7            ;0/1 Master Mode Byte Swap Enable
  24.  
  25. BIT=6            ; Emulation Keyboard Reset Delay Control
  26.                  0=Generate Reset Puls 2µs later
  27.                  1=Generate reset pulse immediately
  28. BIT=5            ;1/0 Parity Check
  29.  
  30. BIT=4            ;0/1 Cache
  31.  
  32. BIT=32           ; Cachesize
  33.                    00= 32KB
  34.                    01= 64KB
  35.                    10= 128KB
  36.                    11= 256KB
  37.  
  38. BIT=10          ; Cache Write Control
  39.                    00=3T state, write hit cycle
  40.                    01=2T state, early write trailing edge delay
  41.                    10=2T state, no early write
  42.                    11=2T state, early write
  43.  
  44. INDEX=22H      ; Shadow RAM Control Register I
  45. ;****************************************************************
  46.  
  47. BIT=7          ; ROM Enable at F0000-FFFFF
  48.                   1=Read from ROM/Write to RAM
  49.                   0=Read/write on RAM and RAM is Write-protected
  50.  
  51. BIT=6          ;0/1 Shadow RAM at D0000h-DFFFFh
  52.  
  53. BIT=5          ;0/1 Shadow RAM at E0000h-EFFFFh
  54.  
  55. BIT=4          ;0/1 Shadow RAM at D0000h-DFFFFh Write Prot
  56.  
  57. BIT=3          ;0/1 Shadow RAM at E0000h-EFFFFh Write Prot
  58.  
  59. BIT=2          ;1/0 Hidden Refresh
  60.  
  61. BIT=1          ;0/1 Ignore A20 Gate (undocumented)
  62.  
  63. BIT=0          ;0/1 Slow Refresh (4 times slower)
  64.  
  65. Index=23H      ;Shadow RAM Control Register II
  66. ;******************************************************************
  67.  
  68. Bit=7          ;0/1 Shadow RAM at EC00h-EFFFh
  69.  
  70. Bit=6          ;0/1 Shadow RAM at E800h-EBFFh
  71.  
  72. Bit=5          ;0/1 Shadow RAM at E400h-E7FFh
  73.  
  74. Bit=4          ;0/1 Shadow RAM at E000h-E3FFh
  75.  
  76. Bit=3          ;0/1 Shadow RAM at DC00h-DFFFh
  77.  
  78. Bit=2          ;0/1 Shadow RAM at D800h-DBFFh
  79.  
  80. Bit=1          ;0/1 Shadow RAM at D400h-D7FFh
  81.  
  82. Bit=0          ;0/1 Shadow RAM at D000h-D3FFh
  83.  
  84. INDEX=24H      ;Index Control Register 1
  85. ;******************************************************************
  86.  
  87. Bit=7654       ;DRAM Typ Bank 0/1
  88.                       0000=B0:256K B1:-
  89.                       0001=B0:256K B1:256K
  90.                       0010=B0:256K B1:1M
  91.                       0011=B0: -   B1: -
  92.                       01xx=B0: -   B1: -
  93.                       1000=B0:1M   B1: -
  94.                       1001=B0:1M   B1:1M
  95.                       1010=B0:1M   B1:4M
  96.                1011=B0:4M   B1:1M
  97.                       1100=B0:4M   B1: -
  98.                       1101=B0:4M   B1:4M
  99.                       111x=B0: -   B1: -
  100.  
  101. Bit=3                 ;unused
  102. Bit=210               ;DRAM Typ Bank 2/3
  103.                       000=B2:1M   B3:-
  104.                       001=B2:1M   B3:1M
  105.                       010=B2: -   B3: -
  106.                       011=B2:4M   B3:1M
  107.                       100=B2:4M   B3: -
  108.                       101=B2:4M   B3:4M
  109.                       11X=B2: -   B3: -
  110.  
  111. INDEX=25H      ; DRAM Control Register II
  112. ;****************************************************************
  113.  
  114. BIT=76         ; Read Cycle Wait States
  115.                        00= 2 Waits
  116.                        01= 3 Waits
  117.                        10= 4 Waits
  118.                        11= 5 Waits
  119. BIT=543        ; Write Cycle Wait States
  120.                        000= 2 Waits
  121.                        001= 2 Waits
  122.                        010= 3 Waits
  123.                        011= 3 Waits
  124.                        100= 4 Waits
  125.                        110= 5 Waits
  126.                        101= ???
  127.                        111= ???
  128.  
  129. BIT=210        ; unused
  130.  
  131. INDEX=26H      ; Shadow RAM Control Register III
  132. ;****************************************************************
  133.  
  134. BIT=7         ;  unused
  135.  
  136. BIT=6         ; Shadow RAM Copy enable for address area C0000h-EFFFFh
  137.                 0=Read/write at AT-Bus
  138.                 1=Read from AT-Bus, Write into  Shadow RAM
  139.  
  140. BIT=5         ;Shadow Write protect at address area C0000h-CFFFFh
  141.                0=Disabled
  142.                1=Enabled
  143.  
  144. BIT=4         ;0/1 Shadow RAM at C0000h-CFFFFFh
  145.  
  146. BIT=3         ;0/1 Shadow RAM at CC000h-CFFFFFh
  147.  
  148. BIT=2         ;0/1 Shadow RAM at C8000h-CBFFFFh
  149.  
  150. BIT=1         ;0/1 Shadow RAM at C4000h-C7FFFFh
  151.  
  152. BIT=0         ;0/1 Shadow RAM at C0000h-C3FFFFh
  153.  
  154. INDEX=27H     ; Control Register 3
  155. ;****************************************************************
  156.  
  157. BIT=7         ; Cacheable Function
  158.               0=DRAM Cacheable controlled by Bit 3-0
  159.               1=all DRAM are NON-cacheable
  160.  
  161. BIT=65        ; Unused
  162.  
  163. BIT=4         ; VIDEO BIOS at C0000h-C8000h area non-cacheable
  164.               0=Cacheable
  165.               1=Non-Cacheable
  166.  
  167. BIT=3210      ; Cacheable Address-Range
  168. ;                   32K-Cache: 8MB,  64K-Cache: 16MB,
  169. ;                  128K-Cache:32MB, 256K-Cache: 64MB
  170.               0000=0..64MB
  171.               0001=0.. 4MB
  172.               0010=0.. 8MB
  173.               0011=0..12MB
  174.               0100=0..16MB
  175.               0101=0..20MB
  176.               0110=0..24MB
  177.               0111=0..28MB
  178.               1000=0..32MB
  179.               1001=0..36MB
  180.               1010=0..40MB
  181.               1011=0..44MB
  182.               1100=0..48MB
  183.               1101=0..52MB
  184.               1110=0..56MB
  185.               1111=0..60MB
  186.  
  187. INDEX=28H  ; Non-Cacheable Block 1 Register I
  188. ;****************************************************************
  189.  
  190. BIT=765    ; Size of Non-cacheable Memory Block 1
  191.             000=64K
  192.             001=128K
  193.             010=256K
  194.             011=512K
  195.             1xx=Disabled
  196. BIT=432    ; Unused
  197.  
  198. BIT=10     ;Address-Bits of non Cacheable Memory Block 1
  199.            xx=A25..A24
  200.  
  201. INDEX=29H  ; Non-Cacheable Block 1 Register II
  202. ;****************************************************************
  203.  
  204. BIT=76543210 ; Address-Bits of non Cacheable Memory Block 1
  205.              xxxxxxxx=A23..A16
  206.  
  207. INDEX=2AH  ; Non-Cacheable Block 2 Register I
  208. ;****************************************************************
  209.  
  210. BIT=765    ; Size of Non-cacheable Memory Block 1
  211.             000=64K
  212.             001=128K
  213.             010=256K
  214.             011=512K
  215.             1xx=Disabled
  216. BIT=432    ; Unused
  217.  
  218. BIT=10     ;A25..A24 Address-Bits of non Cacheable Memory Block 1
  219.  
  220. INDEX=2BH  ; Non-Cacheable Block 2 Register II
  221. ;****************************************************************
  222.  
  223. BIT=76543210 ; A23..A16 of non Cacheable Memory Block 1
  224.  
  225.