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CX686.CFG
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1996-11-26
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9KB
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268 lines
;**********************************************************
; Chipsatz-Konfiguration für Cyrix 6x86 (M1)
; c't 4/96, Andreas Stiller
;**********************************************************
INDEXPORT=22h
DATENPORT=23h
MACRO OPEN = 22h:$C3, 23h:0001xxxx ;; OPEN always direct
MACRO CLOSE = 22h:$C3, 23h:0000xxxx ;; CLOSE always direct
;**********************************************************
CR0 ; Prozessor Controll Register 0
;**********************************************************
BIT=30 ; L1-Cache CD
0=enabled
1=freeze
BIT=29 ; L1 Cache ND, may be locked by C2h:2
1=Write Through
0=Write Back
BIT=18 ;0/1 Alignment Check
BIT=16 ;0/1 Write Protect
;**********************************************************
INDEX=C0h; Configuration Control Register 1
;**********************************************************
Bit=1 ;640KB-1 MByte
0= cacheable
1=non cacheable
;**********************************************************
INDEX=C1h; Configuration Control Register 1
;**********************************************************
Bit=7 ;0/1 SMM Address Space Region 3
Bit=4 ;0/1 NO_Lock
654 ; reserved
Bit=2 ;0/1 SMAC Access System Management Memory
Bit=1 ;0/1 USE_SMI SMM, output pin /SMADS, input /SMI
Bit=0 ;reserved
;**********************************************************
INDEX=C2h; Configuration Control Register 2
;**********************************************************
BIT=7 ;0/1 (SUSP) Suspend Pins (/SUSP und /SUSPA)
BIT=65 ;reserved
BIT=4 ;(WPR1) Cacheble Memory access to 640..1M
0= Not write protected
1= write protected
BIT=3 ;0/1 (HALT) Suspend on Halt
BIT=2 ;0/1 (LOCK) Prohibit Changing of the NW-Bit in CR0
BIT=1,0 ;reserved
;**********************************************************
INDEX=C3h; Configuration Control Register 3
;**********************************************************
BIT=7654 ;(MAPEN) MAP Enable
0000= Accessible only C0-CFh, FEh-FFh
0001= All Configuration registers are accessible
Else= not Valid with current 6x86-Version
BIT=3 ;reserved
BIT=2 ;0/1 (LINBRST) linear address sequence for Burst Cycles
BIT=1 ;0/1 (NMI) during SMM
BIT=0 ;(SMI-LOCK)
0= disabled
1= CCR1 Bits 1,2,3,7 locked
CCR3 Bits 0,1 locked
SMAR-Bits locked
;**********************************************************
INDEX=E8h; Configuration Control Register 4
;**********************************************************
BIT=7 ;0/1 CPUID
BIT=65 ;reserved
BIT=4 ;0/1 (DTE_EN) Directory Table Entry Cache
BIT=3 ;reserved
BIT=210 ;I/O-Recovery Time
000=1 Clock Delay (actual=8 Clock)
001=2 Clock Delay (actual=8 Clock)
010=4 Clock Delay (actual=8 Clock)
011=8 Clock Delay (actual=8 Clock)
100=16 Clock Delay
101=32 Clock Delay
110=64 Clock Delay
111= no Delay
;**********************************************************
INDEX=E9h; Configuration Control Register 5
;**********************************************************
BIT=76 ;reserved
BIT=5 ;0/1 (ARREN) ARR-Register
BIT=4 ;0/1 (LBR1) LBA#-Pin aktiv for 640 KB-1 M
BIT=321 ;reserved
BIT=0 ;(WT-ALLOC) Write-Through Allocate
0= Cachefill only for read miss
1= Cachefill for read and write miss
;**********************************************************
INDEX=C6h/C5h/C4h ;ARR0
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
INDEX=DCh; Region Control 0 for ARR0
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
;**********************************************************
INDEX=C9h/C8h/C7h ;ARR1
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
INDEX=DDh; Region Control 1 for ARR1
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
;**********************************************************
INDEX=CCh/CBh/CAh ;ARR2
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
INDEX=DEh; Region Control 2 for ARR2
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
;**********************************************************
INDEX=CFh/CEh/CDh ;ARR3
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
INDEX=DFh; Region Control 3 for ARR3
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
INDEX=D2h/D1h/D0h ;ARR4
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
;**********************************************************
INDEX=E0h; Region Control 4 for ARR4
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;0/1 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
INDEX=D5h/D4h/D3h ;ARR5
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
;**********************************************************
INDEX=E1h; Region Control 5 for ARR5
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
INDEX=D8h/D7h/D6h ;ARR6
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(2<x) KByte ;; Size= 2 hoch x
;**********************************************************
INDEX=E2h; Region Control 6 for ARR6
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;1/0 (RCD) Caching
INDEX=DBh/DAh/D9h ;ARR7
BIT$=23..04 ;Segment
$xxxxx= ab ^dez(x*4) KByte ; Startadr in KB
BIT$=03..00 ; Size
0000= disabled
else= ^dez(128<x) KByte ;; Size= 2 hoch x
;**********************************************************
INDEX=E3h; Region Control 7 for ARR7
;**********************************************************
BIT=76 ; reserved
BIT=5 ;1/0 (NLB) LBA#
BIT=4 ;1/0 (WT) Write Back
BIT=3 ;0/1 (WG) Write Gathering
BIT=2 ;0/1 (WL) Weak Locking
BIT=1 ;0/1 (WWO) Weak Write Ordering
BIT=0 ;0/1 (RCE) Caching
INDEX=FCh ; undocumented
INDEX=FDh ; undocumented
INDEX=FEh ;(DIR0) Device Identification
BIT=76543210 ;
$1A = cx486DX
$1D = cx486DX/2
0010xxxx = Cyrix 5x86 (M1SC)
0011xxxx = Cyrix 6x86 (M1)
else = unbekannter Prozessortyp
INDEX=FFh ; (DIR1) Device Identification 1
BIT=7654 ; Revision Identification
BIT=3210 ; Stepping Identification
;********************************************************************