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Magazyn Enter 1999 January
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ctchip34
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CX586.CFG
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1995-10-02
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4KB
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108 lines
;********************************************
; Chipsatz-Konfiguration für Cyrix 5x86 (M1SC)
;********************************************
INDEXPORT=22h
DATENPORT=23h
MACRO OPEN = 22h:$C3, 23h:0001xxxx ;; OPEN immer direct
MACRO CLOSE = 22h:$C3, 23h:0000xxxx ;; CLOSE immer direct
;**********************************************************
CR0 ; Prozessor Controll Register 0
;**********************************************************
BIT=30 ; L1-Cache CD
0=enabled
1=freeze
BIT=29 ; L1 Cache ND, may be locked by C2h:2
0=Write Through
1=Write Back
BIT=18 ;0/1 Alignment Check
BIT=16 ;0/1 Write Protect
INDEX=C1h; Configuration Control Register 1
Bit=7654 ; reserved
Bit=3 ;0/1 MMAC SMI-Service to Main Memory Access
Bit=2 ;0/1 SMAC SMM Access with /SMADS output aktive
Bit=1 ;0/1 SMI SMM, output pin /SMADS, input /SMI
Bit=0 ;reserved
INDEX=C2h; Configuration Control Register 2
BIT=7 ;0/1 (SUSP) Suspend Pins (/SUSP und /SUSPA)
BIT=6 ;0/1 (BWRT) Burst Write Cycles
BIT=5 ;reserved
BIT=4 ;0/1 (WT1) Memory access to 640..1M always Write Thru
BIT=3 ;0/1 (HALT) Suspend on Halt
BIT=2 ;0/1 (LOCK) Prohibit Changing of the NW-Bit in CR0
BIT=1 ;0/1 (WBAK) Write Back Cache Interface Pins
BIT=0 ;reserved
INDEX=C3h; Configuration Control Register 3
BIT=7654 ;(MAPEN) Select active Config Register Set for D0h..FDh
0001= Default
Else= not Valid with current 5x86-Version
BIT=3 ;0/1 (SMIAct) Intel compatible SMM (486SL)
BIT=2 ;0/1 (LINBRST) linear address sequence for Burst Cycles
BIT=1 ;0/1 (NMI) during SMM
BIT=0 ;(SMI-LOCK)
0= disabled
1= CCR1 Bits 1,2,3,7 locked
CCR3 Bits 0,1 locked
SMAR-Bits locked
INDEX=E8h; Configuration Control Register 4
BIT=76 ; reserved
BIT=5 ;0/1 (FP_FAST) Fast FPU exception reporting
BIT=4 ;0/1 (DTE_EN) Directory Table Entry Cache
BIT=3 ;0/1 (MEM_BYP) memory bypassing
BIT=210 ;I/O-Recovery Time
xxx=^dez (x) Bus clock cycles
INDEX=F0h; Configuration Register
BIT=7 ;1/0 Self-modifying code checking
BIT=6543 ;Reserved
BIT=2 ;CORE CLK
0=normal
1=1/2 external bus frequency, if bus is idle
BIT=10 ;Clock Mode Core/bus
INDEX=20h; Chip Debug Register
BIT=7 ;Load/Store ordering
0=weak
1=strong
BIT=6 ;0/1 BTB Test Register
BIT=5 ;reserved
BIT=4 ;0/1 Reordering of locked misaligned loads
BIT=3 ;0/1 All instructions stalled to serialize Pipeline
BIT=2 ;0/1 Loopmode
BIT=1 ;0/1 Branch Target Buffer
BIT=0 ;0/1 Return Stack
INDEX=CDh; ;(SMAR) System Memory Address Register;
BIT=7654321 ; A31 - A24 of SMM Address
INDEX=CEh; ;(SMAR) System Memory Address Register;
BIT=7654321 ; A23 - A16 of SMM Address
INDEX=CFh; ;(SMAR) System Memory Address Register;
BIT=7654 ; A15 - A12 of SMM Address
BIT=3210 ; Size 4KB *2^n
INDEX=FEh ;(DIR0) Device Identification
BIT=76543210 ;
$1A = cx486DX
$1D = cx486DX/2
0010xxxx = Cyrix 5x86 (M1SC)
0011xxxx = Cyrix 6x86 (M1)
else = unbekannter Prozessortyp
INDEX=FFh ; (DIR1) Device Identification 1
BIT=7654 ; Revision Identification
BIT=3210 ; Stepping Identification
INDEX=60h ; unknown Register
INDEX=61h ; unknown Register
;********************************************************************