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1987-08-26
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87 lines
Title 7-Bit I/O Port with Handshake Logic
Pattern Port.pds
Revision A
Author Sadahiro Horiko / Kelvin Chow
Company Monolithic Memories Inc., Santa Clara, Ca
Date 3/1/85
CHIP IOPORT PAL20RA10
PL D0 D1 D2 D3 D4 D5 D6 CE DCLK CLR GND
OE DACK DRDY NC Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC
EQUATIONS
Q0 := D0 ;LSB of 7-bit regs
Q0.CLKF = DCLK ;External clock
Q0.SETF = CLR ;Clear register
Q0.TRST = CE ;Tristate control
Q1 := D1 ;Data 1
Q1.CLKF = DCLK ;External clock
Q1.SETF = CLR ;Clear register
Q1.TRST = CE ;Tristate control
Q2 := D2 ;Data 2
Q2.CLKF = DCLK ;External clock
Q2.SETF = CLR ;Clear register
Q2.TRST = CE ;Tristate control
Q3 := D3 ;Data 3
Q3.CLKF = DCLK ;External clock
Q3.SETF = CLR ;Clear register
Q3.TRST = CE ;Tristate control
Q4 := D4 ;Data 4
Q4.CLKF = DCLK ;External clock
Q4.SETF = CLR ;Clear register
Q4.TRST = CE ;Tristate control
Q5 := D5 ;Data 5
Q5.CLKF = DCLK ;External clock
Q5.SETF = CLR ;Clear register
Q5.TRST = CE ;Tristate control
Q6 := D6 ;Data 6
Q6.CLKF = DCLK ;External clock
Q6.SETF = CLR ;Clear register
Q6.TRST = CE ;Tristate control
DRDY := GND ;Handshake logic
DRDY.CLKF = DACK ;Cleared by DACK
DRDY.RSTF = DCLK ;Clear
DRDY.SETF = CLR ;Asserted by DCLK
DRDY.TRST = VCC ;(External clock)
SIMULATION
TRACE_ON CLR Q0 Q1 Q2 Q3 Q4 Q5 Q6 DCLK DRDY DACK
SETF PL /CE /OE /D0 D1 /D2 D3 /D4 D5 /D6 CLR /DCLK /DACK
;Set input values
;Tristate outputs
SETF CE OE CLR ;Remove the tri-
;states on the
;outputs and clear
;registers
SETF CLR
SETF CLR
SETF /CLR ;Clock the data &
SETF DCLK ;set DRDY register
SETF DCLK
SETF /DCLK ;Remove the clock
SETF DACK ;Assert DACK
SETF DACK
SETF /DACK ;Lower DACK
SETF /DACK
TRACE_OFF