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pipeline.pds
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Text File
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1987-08-26
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6KB
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154 lines
TITLE PIPELINE CONTROLLER.
PATTERN 01.
REVISION 01.
AUTHOR CHRIS JAY.
COMPANY MMI SANTA CLARA, CA.
DATE 20TH AUGUST 1986.
;
;THE PAL16R8D HAS BEEN DESIGNED AS A VERY HIGH
;SPEED CONTROLLER FOR AN INSTRUCTION PIPELINE
;IN A HIGH SPEED PROCESSOR SYSTEM. THE PAL WILL
;CONTROL THE FLOW OF INSTRUCTIONS IN A FOUR DEEP
;PIPELINE. THE REGISTERS MAY BE EXPANDED TO ANY
;REALISTC WIDTH; 8 BITS, 16 BITS, 32 BITS ETC.
;TO RESET THE DEVICE, THE /RST LINE IS HELD LOW
;FOR TWO CLOCK PERIODS, THE EMPTY AND RDY REGISTERS
;WILL WILL INDICATE THAT THE PIPELINE IS EMPTY
;AND READY FOR THE FIRST WRITE SEQUENCE.
;THE INSTRUCTIONS MAY BE WRITTEN INTO THE PIPELINE
;IN A SEQUENCE OF FOUR. THE REQUEST TO WRITE LINE IS
;ASSERTED HIGH WHEN THE FIRST INSTRUCTION IS
;VALID, AND IS CLOCKED INTO THE PAL AS THE ENABLE
;WRITE SIGNAL. THE ENABLE LOAD GOES HIGH TO
;ENABLE THE FIRST SYNCHRONOUS LOAD, AND THE RDY
;OUTPUT GOES INACTIVE LOW. QA AND QB REPRESENT AN
;ON CHIP UP/DOWN COUNTER WHICH IS INCREMENTED AFTER
;THE FIRST LOAD. THE RDY LINE GOES ACTIVE AGAIN
;TO INDICATE THAT THE PIPELINE IS READY TO
;RECIEVE THE SECOND INSTRUCTION, THE ENABLE LOAD
;OUTPUT GOES INACTIVE LOW. SUCCESSIVE LOADS MAY TAKE
;PLACE ON THIS `HANDSHAKE' BASIS UNTIL ALL FOUR
;PIPELINE REGISTERS ARE LOADED, THEN THE FULL
;REGISTER GOES HIGH THE PIPLINE IS FULL AND READY
;TO BE EMPTIED. TO READ DATA THE RD INPUT
;IS ASSERTED AND REGISTERED IN THE ERD, ENABLE
;READ REGISTER. THE FIRST INSTRUCTION IS TAKEN
;OUT OF THE PIPELINE, THE FULL FLAG GOES INACTIVE
;LOW AND THE INTERNAL COUNTER IS DECREMENTED AS
;EACH INSTRUCTION TAKEN OUT OF THE PIPELINE. WHEN
;FOUR READS HAVE ZERO'D THE COUNTER AND SET THE
;EMPTY FLAG REGISTER ACTIVE, THE PIPELINE IS EMPTY
;AND READY FOR A NEW WRITE CYCLE.
;
; PIN DESCRIPTION
;
;PIN 1...CK.....SYNCHRONISING CLOCK.
;PIN 2.../RST...ACTIVE LOW FOR SYNCHRONOUS RESET.
;PIN 3...WRT....WRITE HANDSHAKE INPUT. HIGH FOR REQUEST
; TO WRITE.
;PIN 9...RD.....HAND SHAKE ACTIVE HIGH TO READ.
;PIN 10..GND.
;PIN 11../OE....ACTIVE LOW OUTPUT ENABLE.
;PIN 12..FULL...ACTIVE HIGH FULL FLAG.
;PIN 13..QA.....COUNTER REGISTER LSB.
;PIN 14..QB.....COUNTER REGISTER MSB.
;PIN 15..EWT....ENABLE WRITE FLAG HIGH IN ACTIVE REQUEST
; TO THE WRITE INPUT.
;PIN 16..ENLD...ENABLE LOAD ACTIVE HIGH OUTPUT TO ENABLE
; THE PIPELINE REGISTER LOAD.
;PIN 17..ERD....ENABLE READ ACTIVE RESPONSE TO A READ
; REQUEST.
;PIN 18..EMPTY..ACTIVE HIGH WHEN THE REGISTER PIPELINE
; IS EMPTY.
;PIN 19..RDY....HANDSHAKE OUTPUT, GOES ACTIVE HIGH WHEN
; THE PIPELINE REGISTER INPUT IS READY FOR
; THE NEXT INSTRUCTION.
;PIN 20..VCC.
;
;
CHIP PIPECNTRL PAL16R8
;
;PINS 1 2 3 4 5
CK /RST WRT NC NC
;PINS 6 7 8 9 10
NC NC NC RD GND
;PINS 11 12 13 14 15
/OE FULL QA QB EWT
;PINS 16 17 18 19 20
ENLD ERD EMPTY RDY VCC
EQUATIONS
/ENLD := ENLD*EWT ;ENABLE INSTRUCTION
+ ENLD*ERD ;REGISTER LOAD DURING
+ RST ;ACTIVE READ AND WRITE
+ /ERD*/EWT ;DISABLE WHEN READ AND
+ EMPTY*ERD ;WRITE ARE INACTIVE.
;RESET AT POWER UP.
/RDY := /ENLD*EWT*/RST ;THE RDY INPUT FORMS
+ ERD*/RST ;PART OF THE HANDSHAKE.
+ FULL*/RST ;WHEN ACTIVE HIGH THE
;INSTRUCTION REGISTER
;FILE IS READY FOR THE
;NEXT INSTRUCTION.
/QA := QA*ENLD*EWT*/FULL ;INTERNAL UP DOWN
+ /QA*/ENLD*EWT*/FULL ;COUNTER LSB. UP
+ EMPTY ;COUNT FOR WRITE
+ QA*/ENLD*ERD*/FULL ;ACTIVE, DOWN COUNT
+ /QA*ENLD*ERD*/FULL ;FOR ACTIVE READ
+ /QA*/ERD*/EWT*FULL ;HOLD FOR FULL OR
;EMPTY.
/QB := QB*QA*ENLD*EWT*/FULL ;QB IS MSB OF INTERNAL
+ /QB*/ENLD*EWT*/FULL ;REGISTER COUNTER
+ /QB*/QA*EWT*/FULL ;BOTH REGISTERS QA
+ EMPTY ;AND QB REQUIRE TWO
+ QB*/QA*/ENLD*ERD*/FULL ;CLOCK PULSES DURING
+ /QB*QA*ERD*/FULL ;A SYNCHRONOUS RESET.
+ /QB*ENLD*ERD*/FULL ;
+ /QB*/ERD*/EWT*FULL ;
;
/FULL := /QB ;FULL FLAG GOES HIGH
+ /QA ;WHEN COUNT IS MAX
+ RST ;TO INDICATE ALL
+ ERD ;PIPELINE REGISTERS
;ARE FULL.
/EMPTY := QA*/RST ;WHEN PIPLINE HAS BEEN
+ QB*/RST ;FLUSHED INTERNAL
+ EWT*/RST ;COUNTER IS ZERO AND
;EMPTY FLAG IS SET.
/EWT := /WRT ;ENABLE WRITE ONLY IF
+ ERD ;READ IS INACTIVE AND
+ FULL ;PIPELINE IS NOT FULL.
+ RST ;
;
/ERD := /RD ;ENABLE READ FLAG ONLY
+ EWT ;IF WRITE NOT ACTIVE
+ EMPTY ;AND PIPELINE IS NOT
+ RST ;EMPTY.
SIMULATION
TRACE_ON CK WRT RD RST RDY ;TRACE ALL SIGNALS.
ENLD QA QB FULL EMPTY ;
EWT ERD ;
SETF /CK RST OE ;SET INITAL CONDITIONS.
CLOCKF CK ;PERFORM RESET, TWO
CLOCKF CK ;CLOCKS REQUIRED.
SETF /RST /WRT /RD ;IDLE SYSTEM FOR
FOR I := 0 TO 1 DO ;THREE CLOCK CYCLES.
BEGIN CLOCKF CK ;
END ;
SETF WRT /RD ;REQUEST TO 'WRITE TO
CLOCKF CK ;PIPELINE', RESPONSE
FOR I := 0 TO 8 DO ;TO RDY = HIGH. CLOCK
BEGIN CLOCKF CK ;9 CYCLES, TO LOAD
END ;FOUR REGISTERS THEN
SETF RD /WRT ;IDLE.
FOR I := 0 TO 8 DO ;RESPOND TO FULL FLAG
BEGIN CLOCKF CK ;READ FROM THE PIPELINE.
END ;9 CYCLES.
SETF /WRT /RD ;CHECK INACTIVE STATE.
FOR I := 0 TO 1 DO ;TWO CYCLES OF EMPTY
BEGIN CLOCKF CK ;PIPELINE, NO WRITE OR
END ;READ.
TRACE_OFF ;END OF SIMULATION.