home *** CD-ROM | disk | FTP | other *** search
/ messroms.de / 2007-01-13_www.messroms.de.zip / CPU / Z80 < prev    next >
Text File  |  2007-01-13  |  16KB  |  241 lines
  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                            Zilog                             |
  5. |                                                              |
  6. |                 ZZZZZZZ    88888      000                    |
  7. |                      Z    8     8    0   0                   |
  8. |                     Z     8     8   0   0 0                  |
  9. |                    Z       88888    0  0  0                  |
  10. |                   Z       8     8   0 0   0                  |
  11. |                  Z        8     8    0   0                   |
  12. |                 ZZZZZZZ    88888      000                    |
  13. |                                                              |
  14. |          Z80 MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_                  |
  22. |         <-- A11 |_|1                   40|_| A10 -->         |
  23. |                  _|                      |_                  |
  24. |         <-- A12 |_|2                   39|_| A9 -->          |
  25. |                  _|                      |_                  |
  26. |         <-- A13 |_|3                   38|_| A8 -->          |
  27. |                  _|                      |_                  |
  28. |         <-- A14 |_|4                   37|_| A7 -->          |
  29. |                  _|                      |_                  |
  30. |         <-- A15 |_|5                   36|_| A6 -->          |
  31. |                  _|                      |_                  |
  32. |         --> CLK |_|6                   35|_| A5 -->          |
  33. |                  _|                      |_                  |
  34. |         <--> D4 |_|7                   34|_| A4 -->          |
  35. |                  _|                      |_                  |
  36. |         <--> D3 |_|8                   33|_| A3 -->          |
  37. |                  _|                      |_                  |
  38. |         <--> D5 |_|9                   32|_| A2 -->          |
  39. |                  _|                      |_                  |
  40. |         <--> D6 |_|10        Z80       31|_| A1 -->          |
  41. |                  _|                      |_                  |
  42. |             +5V |_|11                  30|_| A0 -->          |
  43. |                  _|                      |_                  |
  44. |         <--> D2 |_|12                  29|_| GND             |
  45. |                  _|                      |_  ____            |
  46. |         <--> D7 |_|13                  28|_| RFSH -->        |
  47. |                  _|                      |_  __              |
  48. |         <--> D0 |_|14                  27|_| M1 -->          |
  49. |                  _|                      |_  _____           |
  50. |         <--> D1 |_|15                  26|_| RESET <--       |
  51. |             ___  _|                      |_  _____           |
  52. |         --> INT |_|16                  25|_| BUSRQ <--       |
  53. |             ___  _|                      |_  ____            |
  54. |         --> NMI |_|17                  24|_| WAIT <--        |
  55. |            ____  _|                      |_  ____            |
  56. |        <-- HALT |_|18                  23|_| BUSAK -->       |
  57. |            ____  _|                      |_  __              |
  58. |        <-- MREQ |_|19                  22|_| WR -->          |
  59. |            ____  _|                      |_  __              |
  60. |        <-- IORQ |_|20                  21|_| RD -->          |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        August 1981                                    |
  78. |Updated        April 1985                                     |
  79. |Issue          1.3                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic  |SZHPNC|Description          |Notes                 |
  83. |----------+------+---------------------+----------------------|
  84. |ADC A,s   |***V0*|Add with Carry       |A=A+s+CY              |
  85. |ADC HL,ss |**?V0*|Add with Carry       |HL=HL+ss+CY           |
  86. |ADD A,s   |***V0*|Add                  |A=A+s                 |
  87. |ADD HL,ss |--?-0*|Add                  |HL=HL+ss              |
  88. |ADD IX,pp |--?-0*|Add                  |IX=IX+pp              |
  89. |ADD IY,rr |--?-0*|Add                  |IY=IY+rr              |
  90. |AND s     |***P00|Logical AND          |A=A&s                 |
  91. |BIT b,m   |?*1?0-|Test Bit             |m&{2^b}               |
  92. |CALL cc,nn|------|Conditional Call     |If cc CALL            |
  93. |CALL nn   |------|Unconditional Call   |-[SP]=PC,PC=nn        |
  94. |CCF       |--?-0*|Complement Carry Flag|CY=~CY                |
  95. |CP s      |***V1*|Compare              |A-s                   |
  96. |CPD       |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
  97. |CPDR      |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
  98. |CPI       |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
  99. |CPIR      |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
  100. |CPL       |--1-1-|Complement           |A=~A                  |
  101. |DAA       |***P-*|Decimal Adjust Acc.  |A=BCD format          |
  102. |DEC s     |***V1-|Decrement            |s=s-1                 |
  103. |DEC xx    |------|Decrement            |xx=xx-1               |
  104. |DEC ss    |------|Decrement            |ss=ss-1               |
  105. |DI        |------|Disable Interrupts   |                      |
  106. |DJNZ e    |------|Dec., Jump Non-Zero  |B=B-1 till B=0        |
  107. |EI        |------|Enable Interrupts    |                      |
  108. |EX [SP],HL|------|Exchange             |[SP]<->HL             |
  109. |EX [SP],xx|------|Exchange             |[SP]<->xx             |
  110. |EX AF,AF' |------|Exchange             |AF<->AF'              |
  111. |EX DE,HL  |------|Exchange             |DE<->HL               |
  112. |EXX       |------|Exchange             |qq<->qq'   (except AF)|
  113. |HALT      |------|Halt                 |                      |
  114. |IM n      |------|Interrupt Mode       |             (n=0,1,2)|
  115. |IN A,[n]  |------|Input                |A=[n]                 |
  116. |IN r,[C]  |***P0-|Input                |r=[C]                 |
  117. |INC r     |***V0-|Increment            |r=r+1                 |
  118. |INC [HL]  |***V0-|Increment            |[HL]=[HL]+1           |
  119. |INC xx    |------|Increment            |xx=xx+1               |
  120. |INC [xx+d]|***V0-|Increment            |[xx+d]=[xx+d]+1       |
  121. |INC ss    |------|Increment            |ss=ss+1               |
  122. |IND       |?*??1-|Input and Decrement  |[HL]=[C],HL=HL-1,B=B-1|
  123. |INDR      |?1??1-|Input, Dec., Repeat  |IND till B=0          |
  124. |INI       |?*??1-|Input and Increment  |[HL]=[C],HL=HL+1,B=B-1|
  125. |INIR      |?1??1-|Input, Inc., Repeat  |INI till B=0          |
  126. |JP [HL]   |------|Unconditional Jump   |PC=[HL]               |
  127. |JP [xx]   |------|Unconditional Jump   |PC=[xx]               |
  128. |JP nn     |------|Unconditional Jump   |PC=nn                 |
  129. |JP cc,nn  |------|Conditional Jump     |If cc JP              |
  130. |JR e      |------|Unconditional Jump   |PC=PC+e               |
  131. |JR cc,e   |------|Conditional Jump     |If cc JR(cc=C,NC,NZ,Z)|
  132. |LD dst,src|------|Load                 |dst=src               |
  133. |LD A,i    |**0*0-|Load                 |A=i            (i=I,R)|
  134. |LDD       |--0*0-|Load and Decrement   |[DE]=[HL],HL=HL-1,#   |
  135. |LDDR      |--000-|Load, Dec., Repeat   |LDD till BC=0         |
  136. |LDI       |--0*0-|Load and Increment   |[DE]=[HL],HL=HL+1,#   |
  137. |LDIR      |--000-|Load, Inc., Repeat   |LDI till BC=0         |
  138. |NEG       |***V1*|Negate               |A=-A                  |
  139. |NOP       |------|No Operation         |                      |
  140. |OR s      |***P00|Logical inclusive OR |A=Avs                 |
  141. |OTDR      |?1??1-|Output, Dec., Repeat |OUTD till B=0         |
  142. |OTIR      |?1??1-|Output, Inc., Repeat |OUTI till B=0         |
  143. |OUT [C],r |------|Output               |[C]=r                 |
  144. |OUT [n],A |------|Output               |[n]=A                 |
  145. |OUTD      |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
  146. |OUTI      |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
  147. |POP xx    |------|Pop                  |xx=[SP]+              |
  148. |POP qq    |------|Pop                  |qq=[SP]+              |
  149. |PUSH xx   |------|Push                 |-[SP]=xx              |
  150. |PUSH qq   |------|Push                 |-[SP]=qq              |
  151. |RES b,m   |------|Reset bit            |m=m&{~2^b}            |
  152. |RET       |------|Return               |PC=[SP]+              |
  153. |RET cc    |------|Conditional Return   |If cc RET             |
  154. |RETI      |------|Return from Interrupt|PC=[SP]+              |
  155. |RETN      |------|Return from NMI      |PC=[SP]+              |
  156. |RL m      |**0P0*|Rotate Left          |m={CY,m}<-            |
  157. |RLA       |--0-0*|Rotate Left Acc.     |A={CY,A}<-            |
  158. |RLC m     |**0P0*|Rotate Left Circular |m=m<-                 |
  159. |RLCA      |--0-0*|Rotate Left Circular |A=A<-                 |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic  |SZHPNC|Description          |Notes                 |
  163. |----------+------+---------------------+----------------------|
  164. |RLD       |**0P0-|Rotate Left 4 bits   |{A,[HL]}={A,[HL]}<- ##|
  165. |RR m      |**0P0*|Rotate Right         |m=->{CY,m}            |
  166. |RRA       |--0-0*|Rotate Right Acc.    |A=->{CY,A}            |
  167. |RRC m     |**0P0*|Rotate Right Circular|m=->m                 |
  168. |RRCA      |--0-0*|Rotate Right Circular|A=->A                 |
  169. |RRD       |**0P0-|Rotate Right 4 bits  |{A,[HL]}=->{A,[HL]} ##|
  170. |RST p     |------|Restart              | (p=0H,8H,10H,...,38H)|
  171. |SBC A,s   |***V1*|Subtract with Carry  |A=A-s-CY              |
  172. |SBC HL,ss |**?V1*|Subtract with Carry  |HL=HL-ss-CY           |
  173. |SCF       |--0-01|Set Carry Flag       |CY=1                  |
  174. |SET b,m   |------|Set bit              |m=mv{2^b}             |
  175. |SLA m     |**0P0*|Shift Left Arithmetic|m=m*2                 |
  176. |SRA m     |**0P0*|Shift Right Arith.   |m=m/2                 |
  177. |SRL m     |**0P0*|Shift Right Logical  |m=->{0,m,CY}          |
  178. |SUB s     |***V1*|Subtract             |A=A-s                 |
  179. |XOR s     |***P00|Logical Exclusive OR |A=Axs                 |
  180. |----------+------+--------------------------------------------|
  181. | F        |-*01? |Flag unaffected/affected/reset/set/unknown  |
  182. | S        |S     |Sign flag (Bit 7)                           |
  183. | Z        | Z    |Zero flag (Bit 6)                           |
  184. | HC       |  H   |Half Carry flag (Bit 4)                     |
  185. | P/V      |   P  |Parity/Overflow flag (Bit 2, V=overflow)    |
  186. | N        |    N |Add/Subtract flag (Bit 1)                   |
  187. | CY       |     C|Carry flag (Bit 0)                          |
  188. |-----------------+--------------------------------------------|
  189. | n               |Immediate addressing                        |
  190. | nn              |Immediate extended addressing               |
  191. | e               |Relative addressing (PC=PC+2+offset)        |
  192. | [nn]            |Extended addressing                         |
  193. | [xx+d]          |Indexed addressing                          |
  194. | r               |Register addressing                         |
  195. | [rr]            |Register indirect addressing                |
  196. |                 |Implied addressing                          |
  197. | b               |Bit addressing                              |
  198. | p               |Modified page zero addressing (see RST)     |
  199. |-----------------+--------------------------------------------|
  200. |DEFB n(,...)     |Define Byte(s)                              |
  201. |DEFB 'str'(,...) |Define Byte ASCII string(s)                 |
  202. |DEFS nn          |Define Storage Block                        |
  203. |DEFW nn(,...)    |Define Word(s)                              |
  204. |-----------------+--------------------------------------------|
  205. | A  B  C  D  E   |Registers (8-bit)                           |
  206. | AF  BC  DE  HL  |Register pairs (16-bit)                     |
  207. | F               |Flag register (8-bit)                       |
  208. | I               |Interrupt page address register (8-bit)     |
  209. | IX IY           |Index registers (16-bit)                    |
  210. | PC              |Program Counter register (16-bit)           |
  211. | R               |Memory Refresh register                     |
  212. | SP              |Stack Pointer register (16-bit)             |
  213. |-----------------+--------------------------------------------|
  214. | b               |One bit (0 to 7)                            |
  215. | cc              |Condition (C,M,NC,NZ,P,PE,PO,Z)             |
  216. | d               |One-byte expression (-128 to +127)          |
  217. | dst             |Destination s, ss, [BC], [DE], [HL], [nn]   |
  218. | e               |One-byte expression (-126 to +129)          |
  219. | m               |Any register r, [HL] or [xx+d]              |
  220. | n               |One-byte expression (0 to 255)              |
  221. | nn              |Two-byte expression (0 to 65535)            |
  222. | pp              |Register pair BC, DE, IX or SP              |
  223. | qq              |Register pair AF, BC, DE or HL              |
  224. | qq'             |Alternative register pair AF, BC, DE or HL  |
  225. | r               |Register A, B, C, D, E, H or L              |
  226. | rr              |Register pair BC, DE, IY or SP              |
  227. | s               |Any register r, value n, [HL] or [xx+d]     |
  228. | src             |Source s, ss, [BC], [DE], [HL], nn, [nn]    |
  229. | ss              |Register pair BC, DE, HL or SP              |
  230. | xx              |Index register IX or IY                     |
  231. |-----------------+--------------------------------------------|
  232. | +  -  *  /  ^   |Add/subtract/multiply/divide/exponent       |
  233. | &  ~  v  x      |Logical AND/NOT/inclusive OR/exclusive OR   |
  234. | <-  ->          |Rotate left/right                           |
  235. | [ ]             |Indirect addressing                         |
  236. | [ ]+  -[ ]      |Indirect addressing auto-increment/decrement|
  237. | { }             |Combination of operands                     |
  238. | #               |Also BC=BC-1,DE=DE-1                        |
  239. | ##              |Only lower 4 bits of accumulator A used     |
  240. ----------------------------------------------------------------
  241.