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  2. |                                                              |
  3. |                                                              |
  4. |                            Zilog                             |
  5. |                                                              |
  6. |       ZZZZZZZ    88888      000       000       000          |
  7. |            Z    8     8    0   0     0   0     0   0         |
  8. |           Z     8     8   0   0 0   0   0 0   0   0 0        |
  9. |          Z       88888    0  0  0   0  0  0   0  0  0        |
  10. |         Z       8     8   0 0   0   0 0   0   0 0   0        |
  11. |        Z        8     8    0   0     0   0     0   0         |
  12. |       ZZZZZZZ    88888      000       000       000          |
  13. |                                                              |
  14. |      Z8001/Z8002 MICROPROCESSOR Instruction Set Summary      |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX    X |
  20. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XX |
  21. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXX |
  22. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXX |
  23. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXX |
  24. | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX  |
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  26. | XXXXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX      |
  27. | XXXXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX        |
  28. | XXXXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX          |
  29. | XXXXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX            |
  30. | XXXXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX              |
  31. | XXXXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX                |
  32. | XXXXXXXXXXXXXXX     XXXXXXXXX     XXXXXXXXX                  |
  33. |                   XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXX |
  34. |                 XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXX |
  35. |               XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXX |
  36. |             XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXX |
  37. |           XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXX |
  38. |         XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXX |
  39. |       XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXX |
  40. |     XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  41. |   XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  42. | XXXXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  43. | XXXXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  44. | XXXXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  45. | XXX     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  46. | X     XXXXXXXXX     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX |
  47. |                                                              |
  48. |                                                              |
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  50. | XXXXXXXXXXXXXXX    XXX   XXXXX                               |
  51. | XXXXXXXXXXXXXXX    XXX   XXXXX                               |
  52. | XXX       XXXX             XXX                               |
  53. |         XXXX    XXXXXX     XXX     XXXXXXX       XXXXXX XX   |
  54. |       XXXX      XXXXXX     XXX   XXXXXXXXXXX   XXXXXXXXXXXXX |
  55. |      XXXX          XXX     XXX  XXXX     XXXX XXXX     XXXX  |
  56. |    XXXX            XXX     XXX  XXX       XXX XXX       XXX  |
  57. |  XXXX       XXX    XXX     XXX  XXXX     XXXX XXXX     XXXX  |
  58. | XXXXXXXXXXXXXXX XXXXXXXX XXXXXXX XXXXXXXXXXX   XXXXXXXXXXXX  |
  59. | XXXXXXXXXXXXXXX XXXXXXXX XXXXXXX   XXXXXXX       XXXXXX XXX  |
  60. |                                                         XXX  |
  61. |                                                 XX     XXXX  |
  62. |                                                XXXXXXXXXXX   |
  63. |                                                  XXXXXXX     |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        October 1981                                   |
  78. |Updated        April 1985                                     |
  79. |Issue          1.2                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic    |CZSPDH|Description                 |Notes        |
  83. |------------+------+----------------------------+-------------|
  84. |ADCb   d,s  |****bb|Add with Carry              |d=d+s+C      |
  85. |ADDa   d,s  |****bb|Add                         |d=d+s        |
  86. |ANDb   d,s  |-**b--|Logical AND                 |d=d&s        |
  87. |BITb   d,s  |-*----|Bit Test                    |Z=~d<s>      |
  88. |CALL   d    |------|Call                        |-[SP]=PC,PC=d|
  89. |CALR   d    |------|Call Relative               |-[SP]=PC,PC=d|
  90. |CLRb   d    |------|Clear                       |d=0          |
  91. |COMb   d    |-**b--|Complement                  |d=~d         |
  92. |COMFLG f    |++++--|Complement Flag             |f=~f         |
  93. |CPa    d,s  |****--|Compare                     |d-s          |
  94. |CPDb   d,s,c|?*?*--|Compare and Decrement       |d-s,r=r-1    |
  95. |CPDRb  d,s,c|?*?*--|Compare, Decrement and Rept |CPD till r=0 |
  96. |CPIb   d,s,c|?*?*--|Compare and Increment       |d-s,r=r+1    |
  97. |CPIRb  d,s,c|?*?*--|Compare, Increment and Rept |CPI till r=0 |
  98. |CPSDb  d,s,c|?*?*--|Compare String and Decrement|d-s,r=r-1    |
  99. |CPSDRb d,s,c|?*?*--|Compare String, Dec. and Rep|CPSD till r=0|
  100. |CPSIb  d,s,c|?*?*--|Compare String and Increment|d-s,r=r+1    |
  101. |CPSIRb d,s,c|?*?*--|Compare String, Inc. and Rep|CPSI till r=0|
  102. |DAB    d    |***---|Decimal Adjust Byte         |d=BCD format |
  103. |DECb   d,s  |-***--|Decrement (s=1-16)          |d=d-s        |
  104. |DI     i    |------|Disable Interrupts          |            #|
  105. |DIVl   d,s  |****--|Divide                      |d=d/s        |
  106. |DbJNZ  r,d  |------|Decrement & Jump if Not Zero|r=r-1        |
  107. |EI     i    |------|Enable Interrupts           |            #|
  108. |EXb    d,s  |------|Exchange                    |d<->s        |
  109. |EXTSa  d    |------|Extend Signs                |             |
  110. |HALT        |------|Halt                        |            #|
  111. |pINb   d,s  |------|(Special) Input             |d=s         #|
  112. |INCb   d,s  |-***--|Increment (s=1-16)          |d=d+s        |
  113. |pINDb  d,s,r|---*--|(Special) Input and Dec.    |d=s,r=r-1   #|
  114. |pINDRb d,s,r|---1--|(Special) Input, Dec. & Rept|IND till r-0#|
  115. |pINIb  d,s,r|---*--|(Special) Input and Inc.    |d=s,r=r+1   #|
  116. |pINIRb d,s,r|---1--|(Special) Input, Inc. & Rept|INI till r=0#|
  117. |IRET        |??????|Interrupt Return            |PS=[SP]+    #|
  118. |JP     cc,d |------|Jump                        |PC=d         |
  119. |JR     cc,d |------|Jump Relative               |PC=d         |
  120. |LDa    d,s  |------|Load                        |d=s          |
  121. |LDA    d,s  |------|Load Address                |d=EAs        |
  122. |LDAR   d,s  |------|Load Address Relative       |d=EAs        |
  123. |LDCTL  d,s  |++++++|Load Control                |d=s         #|
  124. |LDCTLB d,s  |++++++|Load Control Byte           |d=s          |
  125. |LDDb   d,s,r|---*--|Load and Decrement          |d=s,r=r-1    |
  126. |LDDRb  d,s,r|---1--|Load, Decrement and Repeat  |LDD till r=0 |
  127. |LDIb   d,s,r|---*--|Load and Increment          |d=s,r=r+1    |
  128. |LDIRb  d,s,r|---1--|Load, Increment and Repeat  |LDI till r=0 |
  129. |LDK    d,s  |------|Load Constant (s=0-15)      |d=s          |
  130. |LDM    d,s,n|------|Load Multiple (n=1-16)      |d=s (n words)|
  131. |LDPS   s    |??????|Load Program Status         |PS=s        #|
  132. |LDRa   d,s  |------|Load Relative               |d=s          |
  133. |MBIT        |??*???|Multi-Micro Bit Test        |S=~MI pin   #|
  134. |MREQ   d    |-**---|Multi-Micro Request         |S=available #|
  135. |MRES        |------|Multi-Micro Reset           |~MI=high    #|
  136. |MSET        |------|Multi-Micro Set             |~MO=low     #|
  137. |MULTl  d,s  |***0--|Multiply                    |d=d*s        |
  138. |NEGb   d    |****--|Negate                      |d=-d         |
  139. |NOP         |------|No Operation                |             |
  140. |ORb    d,s  |-**b--|Logical inclusive OR        |d=dvs        |
  141. |pOTDRb d,s,r|---1--|(Special) Output, Dec. & Rep|OTD till r=0#|
  142. |pOTIRb d,s,r|---1--|(Special) Output, Inc. & Rep|OTI till r=0#|
  143. |pOUTb  d,s  |------|(Special) Output            |d=s         #|
  144. |pOUTDb d,s,r|---*--|(Special) Output and Dec.   |d=s,r=r=1   #|
  145. |pOUTIb d,s,r|---*--|(Special) Output and Inc.   |d=s,r=r+1   #|
  146. |POPl   d,s  |------|Pop                         |d=s,[EAs]+   |
  147. |PUSHl  d,s  |------|Push                        |-[EAs],d=s   |
  148. |RESb   d,s  |------|Reset Bit                   |d<s>=0       |
  149. |RESFLG f    |++++--|Reset Flag                  |f=0          |
  150. |RET    cc   |------|Return                      |PC=[SP]+     |
  151. |RLb    d,s  |****--|Rotate Left                 |d=d<-s       |
  152. |RLCb   d,s  |****--|Rotate Left through Carry   |d={C,d}<-s   |
  153. |RLDB   ll,s |-*?---|Rotate Left Digit Byte      |s={ll,s}<-4  |
  154. |RRb    d,s  |****--|Rotate Right                |d=s->d       |
  155. |RRCb   d,s  |****--|Rotate Right through Carry  |d=s->{C,d}   |
  156. |RRDB   ll,s |-*?---|Rotate Right Digit Byte     |s=4->{ll,s}  |
  157. |SBC    d,s  |****bb|Subtract with Carry         |d=d-s-C      |
  158. |SC     s    |------|System Call (-[SP]={PS,ins})|PS=sys PS   #|
  159. |SDAa   d,s  |****--|Shift Dynamic Arithmetic    |d={1,d,0}<-s |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic    |CZSPDH|Description                 |Notes        |
  163. |------------+------+----------------------------+-------------|
  164. |SDLa   d,s  |***?--|Shift Dynamic Logical       |d={0,d,0}<-s |
  165. |SETb   d,s  |------|Set Bit                     |d<s>=1       |
  166. |SETFLG f    |++++--|Set Flag                    |f=1          |
  167. |SLAa   d,s  |****--|Shift Left Arithmetic       |d={d,0}<-s   |
  168. |SLLa   d,s  |***?--|Shift Left Logical          |d={d,0}<-s   |
  169. |SRAa   d,s  |***0--|Shift Right Arithmetic      |d=s->{1,d}   |
  170. |SRLa   d,s  |***?--|Shift Right Logical         |d=s->{0,d}   |
  171. |SUBa   d,s  |****bb|Subtract                    |d=d-s        |
  172. |TCCb   cc,d |------|Test Condition Code         |If cc d<0>=1 |
  173. |TESTa  d    |-***--|Test                        |dv0          |
  174. |TRDB   d,s,r|-?-*--|Translate and Decrement     |d=s[d],r=r-1 |
  175. |TRDRB  d,s,r|-?-1--|Translate, Dec. and Repeat  |TRDB till r=0|
  176. |TRIB   d,s,r|-?-*--|Translate and Increment     |d=s[d],r=r+1 |
  177. |TRIRB  d,s,r|-?-1--|Translate, Inc. and Repeat  |TRIB till r=0|
  178. |TRTDB  s,s,r|-*-*--|Translate, Test and Dec.    |RH1=s2[s1],..|
  179. |TRTDRB s,s,r|-*-*--|Translate, Test, Dec. & Rept|TRTDB till...|
  180. |TRTIB  s,s,r|-*-*--|Translate, Test and Inc.    |RH1=s2[s1],..|
  181. |TRTIRB s,s,r|-*-*--|Translate, Test, Inc. & Rept|TRTIB till...|
  182. |TSETb  d    |--*---|Test and Set                |{S,d}=d<MSB> |
  183. |XOR    d,s  |-**b--|Logical Exclusive OR        |d=dxs        |
  184. |------------+------+----------------------------+-------------|
  185. | FCW        |-*01? |Unaffected/affected/reset/set/unknown     |
  186. |            |+b    |Optionally affected/affected for byte only|
  187. | C          |C     |Carry flag (Bit 7)                        |
  188. | Z          | Z    |Zero flag (Bit 6)                         |
  189. | S          |  S   |Sign flag (Bit 5)                         |
  190. | D          |   D  |Decimal adjust flag (Bit 4)               |
  191. | P/V        |    P |Parity/Overflow flag (Bit 3)              |
  192. | H          |     H|Half carry flag (Bit 2)                   |
  193. |-------------------+------------------------------------------|
  194. | #n  #nn  #nnnn    |Immediate data mode (IM, 4/8/16/32-bit)   |
  195. | r                 |Register addressing mode (R)              |
  196. | @r                |Indirect Register mode (IR)               |
  197. | <<n>>nn  nn  |nn| |Direct Addressing mode (DA)               |
  198. | <<n>>nn[Rn] nn[Rn]|Indexed Addressing mode (X, not R0)       |
  199. | $+nn  nn          |Relative Addressing mode (RA)             |
  200. | RRn[#nn]          |Based Addressing mode (BA, not RR0)       |
  201. | RRn[Rn]           |Based Indexed addressing mode (BX, not R0)|
  202. |-------------------+------------------------------------------|
  203. |AVAL nnnn(,...)    |Define Address Value(s)                   |
  204. |BVAL n(,...)       |Define Byte Value(s)                      |
  205. |EVEN               |Set program counter to Even address       |
  206. |LVAL nnnn(,...)    |Define Long word Value(s)                 |
  207. |WVAL nn(,...)      |Define Word Value(s)                      |
  208. |-------------------+------------------------------------------|
  209. | FCW               |Flag Control Word (16-bit)                |
  210. | PC                |Program Counter (32-bit)                  |
  211. | PSAP              |Program Status Area Pointer (32-bit)      |
  212. | REFRESH           |Refresh control register (16-bit)         |
  213. | RLn               |Low byte register (8-bit, n=0-7)          |
  214. | RHn               |High byte register (8-bit, n=0-7)         |
  215. | Rn                |Word register (16-bit, n=0-15)            |
  216. | RRn               |Double word register (32-bit, n=0-14,even)|
  217. | RQn               |Quadruple word reg. (64-bit, n=0/4/8/12)  |
  218. | RR14              |Used as stack pointer (32-bit)            |
  219. |-------------------+------------------------------------------|
  220. | a                 |Blank, B or L (Word/Byte/Long operation)  |
  221. | b                 |Blank or B (Word/Byte operation)          |
  222. | c                 |Condition (r,cc)                          |
  223. | cc                |Condition Code (F/Z/NZ/C/NC/PL/MI/NE/EQ/  |
  224. |                   | OV/NOV/PE/PO/GE/LT/GT/LE/UGE/ULT/UGT/ULE)|
  225. | d  d<X>           |Destination/Bit X of Destination          |
  226. | f                 |Flag(s) (C/Z/S/P/V)                       |
  227. | i                 |Interrupt (VI/NVI)                        |
  228. | l                 |Blank or L (Word/Long word operation)     |
  229. | ll                |Link Location (bottom 4 bits of register) |
  230. | n  nn  nnnn       |Constant expression (8/16/32-bit)         |
  231. | p                 |Blank or S (Normal/Special operation)     |
  232. | r                 |Register (RLn/RHn/Rn/RRn/RQn)             |
  233. | s  EAs            |Source/Effective Address of Source        |
  234. | +  -  *  /        |Arithmetic add/subtract/multiply/divide   |
  235. | &  ~  v  x        |Logical AND/NOT/inclusive OR/exclusive OR |
  236. | <-X  X->          |Rotate left/right by X bits               |
  237. | [ ]  [ ]+  -[ ]   |Indirect address/auto-increment/decrement |
  238. | { }  #            |Combination of operands/privileged instr. |
  239. | <<n>>  |nn|       |Segment/short offset (0-255)              |
  240. ----------------------------------------------------------------
  241.