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elxsi.md
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1994-02-06
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;;- Machine description for GNU compiler
;;- Elxsi Version
;; Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
;; This port done by Mike Stump <mrs@cygnus.com> in 1988, and is the first
;; 64 bit port of GNU CC.
;; Based upon the VAX port.
;; This file is part of GNU CC.
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 1, or (at your option)
;; any later version.
;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING. If not, write to
;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
;;- Instruction patterns. When multiple patterns apply,
;;- the first one in the file is chosen.
;;-
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;-
;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
;;- updates for most instructions.
(define_insn ""
[(set (reg:SI 15)
(plus:SI (reg:SI 15)
(match_operand:SI 0 "general_operand" "g")))]
""
"add.64\\t.sp,%0")
(define_insn ""
[(set (reg:SI 15)
(plus:SI (match_operand:SI 0 "general_operand" "g")
(reg:SI 15)))]
""
"add.64\\t.sp,%0")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (reg:SI 15)
(match_operand:SI 1 "general_operand" "g")))]
""
"ld.32\\t%0,.sp\;add.64\\t%0,%1")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (match_operand:SI 1 "general_operand" "g")
(reg:SI 15)))]
""
"ld.32\\t%0,.sp\;add.64\\t%0,%1")
(define_insn ""
[(set (reg:SI 15)
(minus:SI (reg:SI 15)
(match_operand:SI 0 "general_operand" "g")))]
""
"sub.64\\t.sp,%0")
(define_insn ""
[(set (reg:SI 15)
(match_operand:SI 0 "general_operand" "rm"))]
""
"ld.32\\t.sp,%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "m,r")
(reg:SI 15))]
""
"*
if (which_alternative == 0)
return \"st.32\\t.sp,%0\";
return \"ld.32\\t%0,.sp\";
")
; tstdi is first test insn so that it is the one to match
; a constant argument.
(define_insn "tstdi"
[(set (cc0)
(match_operand:DI 0 "register_operand" "r"))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=0;
return \";\\ttstdi\\t%0\";
")
(define_insn "tstdf"
[(set (cc0)
(match_operand:DF 0 "register_operand" "r"))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=0;
return \";\\ttstdf\\t%0\";
")
(define_insn "tstsf"
[(set (cc0)
(match_operand:SF 0 "register_operand" "r"))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=0;
return \";\\ttstsf\\t%0\";
")
(define_insn "cmpdi"
[(set (cc0)
(compare (match_operand:DI 0 "register_operand" "r")
(match_operand:DI 1 "general_operand" "rm")))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=operands[1];
return \";\\tcmpdi\\t%0,%1\";
")
(define_insn "cmpdf"
[(set (cc0)
(compare (match_operand:DF 0 "register_operand" "r")
(match_operand:DF 1 "general_operand" "rm")))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=operands[1];
return \";\\tcmpdf\\t%0,%1\";
")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "general_operand" "rm")))]
""
"*
extern rtx cmp_op0, cmp_op1;
cmp_op0=operands[0]; cmp_op1=operands[1];
return \";\\tcmpsf\\t%0,%1\";
")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(eq (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:eq")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(ne (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:ne")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(le (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:le")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(leu (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmpu.64\\t%0,%1,%2:le")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(lt (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:lt")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(ltu (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmpu.64\\t%0,%1,%2:lt")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(ge (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:ge")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(geu (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmpu.64\\t%0,%1,%2:ge")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(gt (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmp.64\\t%0,%1,%2:gt")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(gtu (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "general_operand" "g")))]
""
"cmpu.64\\t%0,%1,%2:gt")
(define_insn "seq"
[(set (match_operand:DI 0 "register_operand" "=r")
(eq (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"eq\", operands[0]); ")
(define_insn "sne"
[(set (match_operand:DI 0 "register_operand" "=r")
(ne (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"ne\", operands[0]); ")
(define_insn "sle"
[(set (match_operand:DI 0 "register_operand" "=r")
(le (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"le\", operands[0]); ")
(define_insn "sleu"
[(set (match_operand:DI 0 "register_operand" "=r")
(leu (cc0) (const_int 0)))]
""
"* return cmp_set(\"u\", \"le\", operands[0]); ")
(define_insn "slt"
[(set (match_operand:DI 0 "register_operand" "=r")
(lt (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"lt\", operands[0]); ")
(define_insn "sltu"
[(set (match_operand:DI 0 "register_operand" "=r")
(ltu (cc0) (const_int 0)))]
""
"* return cmp_set(\"u\", \"lt\", operands[0]); ")
(define_insn "sge"
[(set (match_operand:DI 0 "register_operand" "=r")
(ge (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"ge\", operands[0]); ")
(define_insn "sgeu"
[(set (match_operand:DI 0 "register_operand" "=r")
(geu (cc0) (const_int 0)))]
""
"* return cmp_set(\"u\", \"ge\", operands[0]); ")
(define_insn "sgt"
[(set (match_operand:DI 0 "register_operand" "=r")
(gt (cc0) (const_int 0)))]
""
"* return cmp_set(\"\", \"gt\", operands[0]); ")
(define_insn "sgtu"
[(set (match_operand:DI 0 "register_operand" "=r")
(gtu (cc0) (const_int 0)))]
""
"* return cmp_set(\"u\", \"gt\", operands[0]); ")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(eq (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "general_operand" "m")))]
""
"cmp.32\\t%0,%1,%2:eq")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(ne (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "general_operand" "m")))]
""
"cmp.32\\t%0,%1,%2:ne")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(le (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "general_operand" "m")))]
""
"cmp.32\\t%0,%1,%2:le")
(define_insn ""
[(set (match_operand:SI 0 "register_operand"