Fresh Fish 4/FreshFish_May-June1994.bin/gnu/info/gcc.info-18

GNU Info File | 1994-02-20 | 49KB | 825 lines

This is Info file gcc.info, produced by Makeinfo-1.55 from the input
file gcc.texi.
   This file documents the use and the internals of the GNU compiler.
   Published by the Free Software Foundation 675 Massachusetts Avenue
Cambridge, MA 02139 USA
   Copyright (C) 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
   Permission is granted to make and distribute verbatim copies of this
manual provided the copyright notice and this permission notice are
preserved on all copies.
   Permission is granted to copy and distribute modified versions of
this manual under the conditions for verbatim copying, provided also
that the sections entitled "GNU General Public License" and "Protect
Your Freedom--Fight `Look And Feel'" are included exactly as in the
original, and provided that the entire resulting derived work is
distributed under the terms of a permission notice identical to this
   Permission is granted to copy and distribute translations of this
manual into another language, under the above conditions for modified
versions, except that the sections entitled "GNU General Public
License" and "Protect Your Freedom--Fight `Look And Feel'", and this
permission notice, may be included in translations approved by the Free
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File: gcc.info,  Node: Obsolete Register Macros,  Prev: Stack Registers,  Up: Registers
Obsolete Macros for Controlling Register Usage
----------------------------------------------
   These features do not work very well.  They exist because they used
to be required to generate correct code for the 80387 coprocessor of the
80386.  They are no longer used by that machine description and may be
removed in a later version of the compiler.  Don't use them!
`OVERLAPPING_REGNO_P (REGNO)'
     If defined, this is a C expression whose value is nonzero if hard
     register number REGNO is an overlapping register.  This means a
     hard register which overlaps a hard register with a different
     number.  (Such overlap is undesirable, but occasionally it allows
     a machine to be supported which otherwise could not be.)  This
     macro must return nonzero for *all* the registers which overlap
     each other.  GNU CC can use an overlapping register only in
     certain limited ways.  It can be used for allocation within a
     basic block, and may be spilled for reloading; that is all.
     If this macro is not defined, it means that none of the hard
     registers overlap each other.  This is the usual situation.
`INSN_CLOBBERS_REGNO_P (INSN, REGNO)'
     If defined, this is a C expression whose value should be nonzero if
     the insn INSN has the effect of mysteriously clobbering the
     contents of hard register number REGNO.  By "mysterious" we mean
     that the insn's RTL expression doesn't describe such an effect.
     If this macro is not defined, it means that no insn clobbers
     registers mysteriously.  This is the usual situation; all else
     being equal, it is best for the RTL expression to show all the
     activity.
`PRESERVE_DEATH_INFO_REGNO_P (REGNO)'
     If defined, this is a C expression whose value is nonzero if
     accurate `REG_DEAD' notes are needed for hard register number REGNO
     at the time of outputting the assembler code.  When this is so, a
     few optimizations that take place after register allocation and
     could invalidate the death notes are not done when this register is
     involved.
     You would arrange to preserve death info for a register when some
     of the code in the machine description which is executed to write
     the assembler code looks at the death notes.  This is necessary
     only when the actual hardware feature which GNU CC thinks of as a
     register is not actually a register of the usual sort.  (It might,
     for example, be a hardware stack.)
     If this macro is not defined, it means that no death notes need to
     be preserved.  This is the usual situation.
File: gcc.info,  Node: Register Classes,  Next: Stack and Calling,  Prev: Registers,  Up: Target Macros
Register Classes
================
   On many machines, the numbered registers are not all equivalent.
For example, certain registers may not be allowed for indexed
addressing; certain registers may not be allowed in some instructions.
These machine restrictions are described to the compiler using
"register classes".
   You define a number of register classes, giving each one a name and
saying which of the registers belong to it.  Then you can specify
register classes that are allowed as operands to particular instruction
patterns.
   In general, each register will belong to several classes.  In fact,
one class must be named `ALL_REGS' and contain all the registers.
Another class must be named `NO_REGS' and contain no registers.  Often
the union of two classes will be another class; however, this is not
required.
   One of the classes must be named `GENERAL_REGS'.  There is nothing
terribly special about the name, but the operand constraint letters `r'
and `g' specify this class.  If `GENERAL_REGS' is the same as
`ALL_REGS', just define it as a macro which expands to `ALL_REGS'.
   Order the classes so that if class X is contained in class Y then X
has a lower class number than Y.
   The way classes other than `GENERAL_REGS' are specified in operand
constraints is through machine-dependent operand constraint letters.
You can define such letters to correspond to various classes, then use
them in operand constraints.
   You should define a class for the union of two classes whenever some
instruction allows both classes.  For example, if an instruction allows
either a floating point (coprocessor) register or a general register
for a certain operand, you should define a class `FLOAT_OR_GENERAL_REGS'
which includes both of them.  Otherwise you will get suboptimal code.
   You must also specify certain redundant information about the
register classes: for each class, which classes contain it and which
ones are contained in it; for each pair of classes, the largest class
contained in their union.
   When a value occupying several consecutive registers is expected in a
certain class, all the registers used must belong to that class.
Therefore, register classes cannot be used to enforce a requirement for
a register pair to start with an even-numbered register.  The way to
specify this requirement is with `HARD_REGNO_MODE_OK'.
   Register classes used for input-operands of bitwise-and or shift
instructions have a special requirement: each such class must have, for
each fixed-point machine mode, a subclass whose registers can transfer
that mode to or from memory.  For example, on some machines, the
operations for single-byte values (`QImode') are limited to certain
registers.  When this is so, each register class that is used in a
bitwise-and or shift instruction must have a subclass consisting of
registers from which single-byte values can be loaded or stored.  This
is so that `PREFERRED_RELOAD_CLASS' can always have a possible value to
return.
`enum reg_class'
     An enumeral type that must be defined with all the register class
     names as enumeral values.  `NO_REGS' must be first.  `ALL_REGS'
     must be the last register class, followed by one more enumeral
     value, `LIM_REG_CLASSES', which is not a register class but rather
     tells how many classes there are.
     Each register class has a number, which is the value of casting
     the class name to type `int'.  The number serves as an index in
     many of the tables described below.
`N_REG_CLASSES'
     The number of distinct register classes, defined as follows:
          #define N_REG_CLASSES (int) LIM_REG_CLASSES
`REG_CLASS_NAMES'
     An initializer containing the names of the register classes as C
     string constants.  These names are used in writing some of the
     debugging dumps.
`REG_CLASS_CONTENTS'
     An initializer containing the contents of the register classes, as
     integers which are bit masks.  The Nth integer specifies the
     contents of class N.  The way the integer MASK is interpreted is
     that register R is in the class if `MASK & (1 << R)' is 1.