PsL Monthly 1994 February/psl_9403.zip/psl_9403/DOS/UT_SYSTM/LOGV20.ZIP/README.DOC

Text File | 1993-12-01 | 13KB | 264 lines

A $20 LOGIC ANALYZER

Yes that is right if you own a PC compatible computer that has a printer
port, you can have a logic analyzer for $20 (or less depending on what
parts you have lying around).  Our $20 logic analyzer features:

- 5 data channels.

- 8 K byte data buffer.

- 5 bit trigger with don't care states.

- maximum sample rate up to several hundred Khz.

- 5 sample rate selections.

- easy to used PC based software.

- timing and state display modes.

- can be used with a notebook PC as a portable logic analyzer.

Of course these features are not comparable to the latest offerings
from HP, but for thousands of dollars less you can own a very useful
tool.  The maximum sample is not fast enough to use on a typical
microprocessor, but it is fast enough to trouble shoot most I/O control
signals, TTL level serial and devices such as EPROM or GAL programmers.

Building the $20 Logic Analyzer

The only piece that needs to be built is an easy to make probe assembly.
It requires only eight components as listed in the parts list.  The
probe assembly is used to connect the five logic analyzer channels and a
ground path to the circuit being tested.  The assembly is detailed in
figure 1.  Figure 2 shows the connection list and figure 3 shows the pin
out of the male DB-25 connector as view from the rear (solder cup side).
Although only six conductors are actually used having a nine conductor
ribbon cable provides for a grounded conductor between each of the
signal channels.  This makes for a shield between signals and prevents
crosstalk between channels.  The three conductors that do not attach to
mini clips can be cut at the point where the ribbon cable is broken out.
Once the signals are separated there is no longer any concern about
crosstalk.  The 9 conductor ribbon cable can be made from any wider
ribbon cable by stripping some of the conductors off.  The 6 clips that
are connected at the end of the cable should be labeled as shown in
figures 1 and 2.  Once the assembly is complete, it is plugged into the
PC's parallel printer port for use.  The software can be configured to
use either LPT1 or LPT2.

Setting Up the $20 Logic Analyzer Software

The $20 Logic Analyzer is very easy to setup.  Copy the program
LOGIC$20.EXE onto your disk.  Then start the program by typing LOGIC$20
and then Enter at the DOS prompt.  The first time it is run the program
will indicate that it could not find the configuration file LOGIC$20.CFG
- this is OK.  As prompted press any key for the main menu to appear.
Select option F8 - Calibrate from the main menu.  This will create a
proper configuration file for the next time the program is run.  You
will be asked which printer port you wish to use.  Enter 1 or 2
corresponding to either LPT1 or LPT2.  The program will take a second to
determine the maximum sample rate that can be used on that PC.  This
information will automatically be stored in the configuration file.  The
calibration process will need repeated for each different PC the $20
Logic Analyzer is installed on.  That completes the setup.

Using the $20 Logic Analyzer

The $20 Logic Analyzer is easy to use.  Start the program as above.
Connect the mini clip labeled ground to the ground of the circuit being
tested.  Connect the other mini clips to the points of interest in the
circuit.  CAUTION - do NOT connect the clips to any signals that are
outside of the 0 to 5 Volt TTL range, it will damage your printer port.
The programs main menu will appears as in Figure 4.  Use option F1 to
select the trigger condition.  Only bits 0 to 4 are valid, bits 5 to 7
are ignored.  The trigger for each bit can be selected to be a 0, a 1 or
an X.  An X at a given channel position means that you do not care about
the state of that channel as part of the trigger condition.  All Xs
means that a trigger will occur immediately.  A trigger of XXX01XX1
means that a trigger will occur when channel 5 is 0 (TTL low), channel 4
is 1 (TTL high) and channel 0 is 1.  Data would still be acquired on
channels 1 and 2, but it would be ignored when checking for a trigger
condition.  Option F3 allows you to select the sample rate, the options
are the maximum sample (as determined from the calibration routine), and
one half, one quarter, one eighth and one sixteenth of the maximum
sample rate.  The choices are expressed as both the sample rate in Khz
and the sample period in microseconds.  Option F4 starts the data
acquisition, data will be acquired until 4096 samples after a trigger
condition occurs or until a key is pressed.  Option F5 will show the
acquired data in STATE format.  For each sample the state display shows
the clock cycle number relative to the trigger point.  The trigger point
is considered clock cycle zero, the negative numbers are the clock
cycles before the trigger and positive are after the trigger.  The next
number is the time in micro seconds relative to the trigger.  Then the
data is displayed first in hex and then in binary channel 0 the least
significant bit).  You can move forward or backward through the state
display by pressing Pg Up, Pg Dn, Home, End and the numeric pad 5 key
(this may only work with Num Lock active depending on your keyboard).
Pg Up and Pg Dn will move backward or forward one page at a time.  Home
will jump to the first data acquired and End to the last data acquired.
The 5 key will return you back to the trigger point.  A special feature
is the search capabilities, by pressing S you will see the search menu.
Specify the search pattern in the same manner as selecting a trigger
condition (1,0 and X), press return when finished.  Select F (forward
search) or R (reverse search).  The program will search for data that
matches your condition and display that screen of data.  This is a very
powerful feature because of the rather deep 8K data buffer (many
expensive logic analyzers have only 2K deep buffers).  Press ESC to exit
the state display.  Press F6 to enter the timing display (Note - this
requires a CGA or compatible display (EGA or VGA)).  The data will be
displayed in timing diagram format.  There is a cursor at the trigger
point and the state information from the cursor position is displayed at
the top of the screen.  The ESC, Pg Up, Pg Dn, Home, End, numeric 5 key
and the search option work the same way as with the state display.  In
addition the left and right arrow keys can move the cursor back and
forth through the data to display the state information for any point on
display.  F7 the file option on the menu allows you the save and restore
data and setup information (trigger word, clock rate etc.).  You can use
this to save data and view it at another time.  F8 is the calibration
mode described above and F9 gives program information.  Use option F10
to exit the program.

How the $20 Logic Analyzer Works

On most system designs there is a trade off between performing various
functions in hardware or using software.  Typically the software route
has a lower parts cost at the expense of lower performance.  For the 20$
logic analyzer the data acquisition is done in software with the
assistance of the standard hardware that is available on all PCs.  This
is why the cost is so low.  The only special hardware needed is the
inexpensive probe assembly.  The probe assembly plugs into the parallel
printer port of your PC, either LPT1 or LPT2 can be used.

The standard PC printer port has 5 input pins, these of course become
the five channels on the $20 Logic Analyzer.  The 5 inputs are all
present on an input port at either 379H (LPT1) or 279H (LPT2) so they
can be read simultaneously by the logic analyzer software.  The software
can check for a match with the trigger condition and then stop data
acquisition when appropriate.  An 8 K byte block of PC memory forms a
buffer for the data.

The sample rate time base is generated by stealing the PCs time of day
clock hardware during data acquisition. To understand how this works we
need to take a look back at the original PC design.

Since the