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1990-12-13
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.HM A 1 1 1 1 1 1
.H 1 "Appendix for asz80 Frankenstein Assembler"
.H 2 "Pseudo Operations"
.H 3 "Standard Pseudo Operation Mnemonics"
.VL 40 5 1
.LI "End"
END
.LI "File Inclusion"
INCL
INCLUDE
.LI "If"
IF
.LI "Else"
ELSE
.LI "End If"
ENDI
.LI "Equate"
EQU
.LI "Set"
SETEQU
.LI "Org"
ORG
.LI "Reserve Memory"
RESERVE
RMB
.LI "Define Byte Data"
BYTE
DB
FCB
.LI "Define Word Data"
DW
FDB
WORD
.LI "Define String Data"
FCC
STRING
.LI "Define Character Set Translation"
CHARSET
.LI "Define Character Value"
CHARDEF
CHD
.LI "Use Character Translation"
CHARUSE
.LE
.H 3 "Machine Dependent Pseudo Operations"
.H 4 "Instruction Set Selection"
.DS I N
CPU string
.DE
The instruction set can be specified in the source file with the CPU
pseudooperation.
The string, delimited by quotes or apostrophes, is scanned for a
substring which selects which instruction set is used.
When the program is invoked, this operation is performed on the name of
the program, then the -p optional arguement, if any, and then any CPU
statements.
The last one selects the which subset of the instructions the assembler will
accept.
The instruction set can be changed at any place in the source file.
.VL 30 5 1
.LI "Instruction Set"
Substrings
.LI 64180
180
.LI z80
z80
Z80
.LI 8085
85
.LI 8080
80
.LE
.H 2 "Instructions"
.H 3 "Instruction List"
.TS H
;
l l l.
Opcode Syntax Selection Criteria
.sp
.TH
.sp
ADC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRBC
ADC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRDE
ADC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRHL
ADC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRSP
ADC reg8 ',' '(' DREGHL ')' REGISA
ADC reg8 ',' index TSZ80PLUS|DRIX|REGISA
ADC reg8 ',' index TSZ80PLUS|DRIY|REGISA
ADC reg8 ',' reg8 0|REGISA
ADC reg8 ',' topexpr REGISA
.sp
ADD dreg ',' dreg DRDESTHL|DRBC
ADD dreg ',' dreg DRDESTHL|DRDE
ADD dreg ',' dreg DRDESTHL|DRHL
ADD dreg ',' dreg DRDESTHL|DRSP
ADD dreg ',' dreg TSZ80PLUS|DRDESTIX|DRBC
ADD dreg ',' dreg TSZ80PLUS|DRDESTIX|DRDE
ADD dreg ',' dreg TSZ80PLUS|DRDESTIX|DRIX
ADD dreg ',' dreg TSZ80PLUS|DRDESTIX|DRSP
ADD dreg ',' dreg TSZ80PLUS|DRDESTIY|DRBC
ADD dreg ',' dreg TSZ80PLUS|DRDESTIY|DRDE
ADD dreg ',' dreg TSZ80PLUS|DRDESTIY|DRIY
ADD dreg ',' dreg TSZ80PLUS|DRDESTIY|DRSP
ADD reg8 ',' '(' DREGHL ')' REGISA
ADD reg8 ',' index TSZ80PLUS|DRIX|REGISA
ADD reg8 ',' index TSZ80PLUS|DRIY|REGISA
ADD reg8 ',' reg8 0|REGISA
ADD reg8 ',' topexpr REGISA
.sp
AND '(' DREGHL ')'
AND index TSZ80PLUS|DRIX
AND index TSZ80PLUS|DRIY
AND reg8
AND topexpr
.sp
BIT expr ',' '(' DREGHL ')' TSZ80PLUS
BIT expr ',' index TSZ80PLUS|DRIX
BIT expr ',' index TSZ80PLUS|DRIY
BIT expr ',' reg8 TSZ80PLUS
.sp
CALL condition ',' expr CCSELC
CALL condition ',' expr CCSELM
CALL condition ',' expr CCSELNC
CALL condition ',' expr CCSELNZ
CALL condition ',' expr CCSELP
CALL condition ',' expr CCSELPE
CALL condition ',' expr CCSELPO
CALL condition ',' expr CCSELZ
CALL expr
.sp
CCF
.sp
CP '(' DREGHL ')'
CP index TSZ80PLUS|DRIX
CP index TSZ80PLUS|DRIY
CP reg8
CP topexpr
.sp
CPD TSZ80PLUS
.sp
CPDR TSZ80PLUS
.sp
CPI TSZ80PLUS
.sp
CPIR TSZ80PLUS
.sp
CPL
.sp
DAA
.sp
DEC '(' DREGHL ')'
DEC dreg DRBC
DEC dreg DRDE
DEC dreg DRHL
DEC dreg DRSP
DEC dreg TSZ80PLUS|DRIX
DEC dreg TSZ80PLUS|DRIY
DEC index TSZ80PLUS|DRIX
DEC index TSZ80PLUS|DRIY
DEC reg8
.sp
DI
.sp
DJNZ topexpr
.sp
EI
.sp
EX '(' DREGSP ')' ',' dreg DRHL
EX '(' DREGSP ')' ',' dreg TSZ80PLUS|DRIX
EX '(' DREGSP ')' ',' dreg TSZ80PLUS|DRIY
EX dreg ',' dreg EX1DE|EX2HL
EX dreg ',' dreg TSZ80PLUS|EX1AF|EX2AF
.sp
EXX TSZ80PLUS
.sp
HALT
.sp
IM expr TSZ80PLUS|INTSETMODE0
IM expr TSZ80PLUS|INTSETMODE1
IM expr TSZ80PLUS|INTSETMODE2
.sp
IN0 reg8 ',' '(' topexpr ')' TS64180
.sp
IN reg8 ',' '(' REGC ')' TSZ80PLUS
IN reg8 ',' '(' topexpr ')' REGISA
.sp
INC '(' DREGHL ')'
INC dreg DRBC
INC dreg DRDE
INC dreg DRHL
INC dreg DRSP
INC dreg TSZ80PLUS|DRIX
INC dreg TSZ80PLUS|DRIY
INC index TSZ80PLUS|DRIX
INC index TSZ80PLUS|DRIY
INC reg8
.sp
IND TSZ80PLUS
.sp
INDR TSZ80PLUS
.sp
INI TSZ80PLUS
.sp
INIR TSZ80PLUS
.sp
JP '(' dreg ')' DRHL
JP '(' dreg ')' TSZ80PLUS|DRIX
JP '(' dreg ')' TSZ80PLUS|DRIY
JP condition ',' expr CCSELC
JP condition ',' expr CCSELM
JP condition ',' expr CCSELNC
JP condition ',' expr CCSELNZ
JP condition ',' expr CCSELP
JP condition ',' expr CCSELPE
JP condition ',' expr CCSELPO
JP condition ',' expr CCSELZ
JP expr
.sp
JR condition ',' expr CCSELC|TSZ80PLUS
JR condition ',' expr CCSELNC|TSZ80PLUS
JR condition ',' expr CCSELNZ|TSZ80PLUS
JR condition ',' expr CCSELZ|TSZ80PLUS
JR expr TSZ80PLUS
.sp
LD '(' dreg ')' ',' reg8 DRBC|REGISA
LD '(' dreg ')' ',' reg8 DRDE|REGISA
LD '(' dreg ')' ',' reg8 DRHL
LD '(' dreg ')' ',' topexpr DRHL
LD '(' topexpr ')' ',' REGA
LD '(' topexpr ')' ',' dreg DRHL
LD '(' topexpr ')' ',' dreg TSZ80PLUS|DRBC
LD '(' topexpr ')' ',' dreg TSZ80PLUS|DRDE
LD '(' topexpr ')' ',' dreg TSZ80PLUS|DRIX
LD '(' topexpr ')' ',' dreg TSZ80PLUS|DRIY
LD '(' topexpr ')' ',' dreg TSZ80PLUS|DRSP
LD dreg ',' '(' topexpr ')' DRHL
LD dreg ',' '(' topexpr ')' TSZ80PLUS|DRBC
LD dreg ',' '(' topexpr ')' TSZ80PLUS|DRDE
LD dreg ',' '(' topexpr ')' TSZ80PLUS|DRIX
LD dreg ',' '(' topexpr ')' TSZ80PLUS|DRIY
LD dreg ',' '(' topexpr ')' TSZ80PLUS|DRSP
LD dreg ',' dreg TSZ80PLUS|DRHL|DRDESTSP
LD dreg ',' dreg TSZ80PLUS|DRIX|DRDESTSP
LD dreg ',' dreg TSZ80PLUS|DRIY|DRDESTSP
LD dreg ',' topexpr DRBC
LD dreg ',' topexpr DRDE
LD dreg ',' topexpr DRHL
LD dreg ',' topexpr DRSP
LD dreg ',' topexpr TSZ80PLUS|DRIX
LD dreg ',' topexpr TSZ80PLUS|DRIY
LD index ',' expr TSZ80PLUS|DRIX
LD index ',' expr TSZ80PLUS|DRIY
LD index ',' reg8 TSZ80PLUS|DRIX
LD index ',' reg8 TSZ80PLUS|DRIY
LD reg8 ',' '(' dreg ')' DRBC|REGISA
LD reg8 ',' '(' dreg ')' DRDE|REGISA
LD reg8 ',' '(' dreg ')' DRHL
LD reg8 ',' '(' topexpr ')' REGISA
LD reg8 ',' index TSZ80PLUS|DRIX
LD reg8 ',' index TSZ80PLUS|DRIY
LD reg8 ',' reg8
LD reg8 ',' specialr TSZ80PLUS|SPECIALIR|REGISA
LD reg8 ',' specialr TSZ80PLUS|SPECIALRR|REGISA
LD reg8 ',' topexpr
LD specialr ',' REGA TSZ80PLUS|SPECIALIR
LD specialr ',' REGA TSZ80PLUS|SPECIALRR
.sp
LDD TSZ80PLUS
.sp
LDDR TSZ80PLUS
.sp
LDI TSZ80PLUS
.sp
LDIR TSZ80PLUS
.sp
MULT dreg TS64180|DRBC
MULT dreg TS64180|DRDE
MULT dreg TS64180|DRHL
MULT dreg TS64180|DRSP
.sp
NEG TSZ80PLUS
.sp
NOP
.sp
OR '(' DREGHL ')'
OR index TSZ80PLUS|DRIX
OR index TSZ80PLUS|DRIY
OR reg8
OR topexpr
.sp
OTDM TS64180
.sp
OTDMR TS64180
.sp
OTDR TSZ80PLUS
.sp
OTIM TS64180
.sp
OTIMR TS64180
.sp
OTIR TSZ80PLUS
.sp
OUT0 '(' topexpr ')' ',' reg8 TS64180
.sp
OUT '(' REGC ')' ',' reg8 TSZ80PLUS
OUT '(' topexpr ')' ',' reg8 REGISA
.sp
OUTD TSZ80PLUS
.sp
OUTI TSZ80PLUS
.sp
POP dreg DRAF
POP dreg DRBC
POP dreg DRDE
POP dreg DRHL
POP dreg TSZ80PLUS|DRIX
POP dreg TSZ80PLUS|DRIY
.sp
PUSH dreg DRAF
PUSH dreg DRBC
PUSH dreg DRDE
PUSH dreg DRHL
PUSH dreg TSZ80PLUS|DRIX
PUSH dreg TSZ80PLUS|DRIY
.sp
RES expr ',' '(' DREGHL ')' TSZ80PLUS
RES expr ',' index TSZ80PLUS|DRIX
RES expr ',' index TSZ80PLUS|DRIY
RES expr ',' reg8 TSZ80PLUS
.sp
RET
RET condition CCSELC
RET condition CCSELM
RET condition CCSELNC
RET condition CCSELNZ
RET condition CCSELP
RET condition CCSELPE
RET condition CCSELPO
RET condition CCSELZ
.sp
RETI TSZ80PLUS
.sp
RETN TSZ80PLUS
.sp
RIM CPU8085
.sp
RL '(' DREGHL ')' TSZ80PLUS
RL index TSZ80PLUS|DRIX
RL index TSZ80PLUS|DRIY
RL reg8 TSZ80PLUS
.sp
RLA
.sp
RLC '(' DREGHL ')' TSZ80PLUS
RLC index TSZ80PLUS|DRIX
RLC index TSZ80PLUS|DRIY
RLC reg8 TSZ80PLUS
.sp
RLCA
.sp
RLD TSZ80PLUS
.sp
RR '(' DREGHL ')' TSZ80PLUS
RR index TSZ80PLUS|DRIX
RR index TSZ80PLUS|DRIY
RR reg8 TSZ80PLUS
.sp
RRA
.sp
RRC '(' DREGHL ')' TSZ80PLUS
RRC index TSZ80PLUS|DRIX
RRC index TSZ80PLUS|DRIY
RRC reg8 TSZ80PLUS
.sp
RRCA
.sp
RRD TSZ80PLUS
.sp
RST expr
.sp
SBC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRBC
SBC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRDE
SBC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRHL
SBC dreg ',' dreg TSZ80PLUS|DRDESTHL|DRSP
SBC reg8 ',' '(' DREGHL ')' REGISA
SBC reg8 ',' index TSZ80PLUS|DRIX|REGISA
SBC reg8 ',' index TSZ80PLUS|DRIY|REGISA
SBC reg8 ',' reg8 0|REGISA
SBC reg8 ',' topexpr REGISA
.sp
SCF
.sp
SET expr ',' '(' DREGHL ')' TSZ80PLUS
SET expr ',' index TSZ80PLUS|DRIX
SET expr ',' index TSZ80PLUS|DRIY
SET expr ',' reg8 TSZ80PLUS
.sp
SIM CPU8085
.sp
SLA '(' DREGHL ')' TSZ80PLUS
SLA index TSZ80PLUS|DRIX
SLA index TSZ80PLUS|DRIY
SLA reg8 TSZ80PLUS
.sp
SLP TS64180
.sp
SRA '(' DREGHL ')' TSZ80PLUS
SRA index TSZ80PLUS|DRIX
SRA index TSZ80PLUS|DRIY
SRA reg8 TSZ80PLUS
.sp
SRL '(' DREGHL ')' TSZ80PLUS
SRL index TSZ80PLUS|DRIX
SRL index TSZ80PLUS|DRIY
SRL reg8 TSZ80PLUS
.sp
SUB '(' DREGHL ')'
SUB index TSZ80PLUS|DRIX
SUB index TSZ80PLUS|DRIY
SUB reg8
SUB topexpr
.sp
TST '(' DREGHL ')' TS64180
TST reg8 TS64180
TST topexpr TS64180
.sp
TSTIO topexpr TS64180
.sp
XOR '(' DREGHL ')'
XOR index TSZ80PLUS|DRIX
XOR index TSZ80PLUS|DRIY
XOR reg8
XOR topexpr
.TE
.H 3 "Selection Criteria Keywords"
.VL 25 5
.LI CPU8085
Instruction is only implemented for the 8085.
.LI TSZ80PLUS
Instruction is implemented in the z80 and 64180 instruction sets.
.LI TS64180
Instruction is only implemented in the 64180
.LI DRIX
Instruction refers to the IX index register
.LI DRIY
Instruction refers to the IY index register
.LI DRSP
Instruction refers to the Stack Pointer
.LI DRHL
Instruction refers to the HL register
.LI DRDE
Instruction refers to the DE register
.LI DRBC
Instruction refers to the BC register
.LI DRAF
Instruction refers to the AF concatenated register
.LI DRDESTSP
Instruction which refers to two double register operands, uses the Stack
Pointer as the destination.
.LI DRDESTHL
Instruction which refers to two double register operands, uses the HL double
register as the destination.
.LI DRDESTIX
Instruction which refers to two double register operands, uses the IX index
register as the destination.
.LI DRDESTIY
Instruction which refers to two double register operands, uses the IY index
register as the destination.
.LI REGISA
Instruction is restricted to using the A register for an 8 bit register
operand.
.LI CCSELNZ
Instruction uses NonZero condition.
.LI CCSELZ
Instruction uses Zero condition.
.LI CCSELNC
Instruction uses No Carry condition.
.LI CCSELC
Instruction uses Carry condition.
.LI CCSELPO
Instruction uses Parity Odd condition.
.LI CCSELPE
Instruction uses Parity Even condition.
.LI CCSELP
Instruction uses Plus condition.
.LI CCSELM
Instruction uses Minus condition.
.LI EX1AF
First operand of an Ex instruction is the AF register.
.LI EX1DE
First operand of an Ex instruction is the DE register.
.LI EX2AF
Second operand of an Ex instruction is the AF register.
.LI EX2HL
Second operand of an Ex instruction is the HL register.
.LI SPECIALIR
Instruction uses the I special register.
.LI SPECIALRR
Instruction uses the R special register.
.LE
.H 3 "Apostrophes"
The apostrophes in the syntax field are a notation used for the
parser generator and are not put in the assembler source statement.
.H 2 "Notes"
.H 3 "Conditions"
Conditions are represented by the reserved symbols z, nz, nc, pe, po, p, m,
and c, and their uppercase versions.
.H 3 "Indexed Addressing"
Index addressing uses the format "( index register + expression )" where
index register is IX or IY.
.H 3 "Top Expressions"
The syntax of some of the instructions combined with the standard expression
syntax resulted in confusion whether an operand was an expression surrounded
by parenthesis, or a memory reference.
To get around this, the expressions in these ambiguous cases were restricted
to those forms of expression that don't have surrounding parenthesis at the
top level.
Subexpressions may be parenthesized, but only if an operator seperates or
precedes the subexpression.
.DS I N
Example
.SP
ld a, (47h) ; load from memory address 0x47
ld a, +(47h) ; load immediate value 0x47
ld a, ((47h)) ; error
.DE
.H 3 "dreg, reg8, specialr"
Double registers (dreg) are the set of symbols af, bc, de, hl, ix, iy, and sp
and their uppercase versions.
.P
Eight bit registers (reg8) are the set of symbols a, b, c, d, e, h, l, and
their uppercase versions.
.P
Special registers are i, r, I, R.
.H 3 "Bit Numbers"
The bit number expression in the BIT, RES, and SET operations has
to have value defined when the instruction is read in the first pass.
The value must be between 0 and 7.
.H 3 "Reserved Symbols"
.H 4 "Machine Dependent Reserved Symbols"
A
AF
B
BC
C
D
DE
E
H
HL
I
IX
IY
L
M
NC
NZ
P
PE
PO
R
SP
Z
a
af
b
bc
c
d
de
e
h
hl
i
ix
iy
l
m
nc
nz
p
pe
po
r
sp
z
.H 4 "Standard Reserved Symbols"
AND
DEFINED
EQ
GE
GT
HIGH
LE
LOW
LT
MOD
NE
NOT
OR
SHL
SHR
XOR
and
defined
eq
ge
gt
high
le
low
lt
mod
ne
not
or
shl
shr
xor
.TC 1 1 7