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- Path: sparky!uunet!utcsri!ois.db.toronto.edu!fche
- Newsgroups: comp.unix.pc-clone.32bit
- From: fche@db.toronto.edu ("Frank Ch. Eigler")
- Subject: Re: ISA Limitation?
- Message-ID: <92Nov5.164644est.42003@ois.db.toronto.edu>
- cc: fche@db.toronto.edu
- Organization: Department of Computer Science, University of Toronto
- References: <1992Oct22.201908.5288@walter.bellcore.com> <1992Oct25.203602.2387@ksmith.uucp> <BwqMxn.26p@portal.hq.videocart.com> <913@felix.Sublink.Org> <1992Nov5.200108.6921@mdd.comm.mot.com>
- Distribution: na
- Date: 5 Nov 92 21:46:56 GMT
- Lines: 24
-
- kelsey@mdd.comm.mot.com (Joe Kelsey) writes:
-
- > [...]
- >I just got through a very trying experience going from 16MB to 32MB on
- >my 486-33 ISA machine. I ended up swapping out the original
- >motherboard for a newer version. The old motherboard did not have a
- >large enough TAG CACHE to handle beyond 16M address range. It did
- >have 256kB of data cache, but the TAG CACHE couldn't handle more than
- >16M address range. My system booted and ran (Esix 4.0.4), but any
- >programs which happened to get mapped into the upper 16M (common
- >enough when you run a few large X Window programs (xv, emacs, etc.))
- >had simply *horrible* performance, since the processor had to endure
- >the full latency of every access to the 70ns rams!
- > [...]
-
-
- What happens if the cache indeed has only a few address bits in its tag
- RAM, say 22 bits, but physical memory may extend above 2^22 bytes? Are
- there boards that *don't* at least *check* the rest of the bits of CPU
- address lines, thus whose cache tag may falsely match an address above
- 2^22 with one below and return the wrong data?
- --
-
- -- Frank Ch. Eigler -- Comp Eng -- <eigler@ecf.toronto.edu> -- (I'm Brian!)
-