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- From: tomw@orac.asd.sgi.com (Tom Weinstein)
- Newsgroups: comp.sys.ibm.pc.misc
- Subject: Re: Parity error - HALT - a better NMI handler?
- Date: 5 Nov 92 02:26:55
- Organization: Silicon Graphics Inc.
- Lines: 22
- Message-ID: <TOMW.92Nov5022655@orac.asd.sgi.com>
- References: <3132.2404.uupcb@synapse.org>
- Reply-To: tomw@asd.sgi.com
- NNTP-Posting-Host: orac.asd.sgi.com
- In-reply-to: chuck.colford@synapse.org's message of 3 Nov 92 22:18:00 GMT
-
- In article <3132.2404.uupcb@synapse.org>, chuck.colford@synapse.org (Chuck Colford) writes:
-
- > Alas; I am not alone. I am plagued by the occasional parity error too.
- > Chris Granitz recently recanted his story & it sounds all too familier.
- > I'm a H/W engineer, so I've gone through most of what I can check (mem
- > speeds, cache data/tag ram speeds, bus speeds, looked for "pushed
- > parts", etc). Still they persist, but I hate to turn off checking.
-
- > Speeds of 33 MHz and up are challenging & require good design & layout
- > practice. Perhaps all the clone designs do not all allow adequate
- > margins.
-
- I've found that most of the time parity errors are caused by
- mis-configured memory management software. QEMM is especially prone to
- this problem. If you fiddle around with then memory regions you use for
- high memory, it usually fixes the problem.
-
-
-
- --
- Love is a conveyor belt of | Tom Weinstein tomw@orac.esd.sgi.com
- warmth -- Jackie Chan | tomw@bears.ucsb.edu
-