NetNews Usenet Archive 1992 #26/NN_1992_26.iso/spool/comp/sys/amiga/hardware/19527

Text File | 1992-11-14 | 1.6 KB | 38 lines

Newsgroups: comp.sys.amiga.hardware
Path: sparky!uunet!ukma!darwin.sura.net!zaphod.mps.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!bret!ceg
From: [e-mail] (Chuck Goodhart)
Subject: Re: Parity
Message-ID: <[e-mail]>
Keywords: parity RAM errors.
Sender: [e-mail] (Usenet)
Nntp-Posting-Host: hyper-bret.jpl.nasa.gov
Organization: Jet Propulsion Laboratory; Pasadena, CA
References: <[e-mail]>
Date: Fri, 13 Nov 1992 15:55:30 GMT
Lines: 24

In article <[e-mail]> [e-mail]
(Ethan Dicks) writes:
>EDC (Error Detection and Correction) is also known as ECC (why, I don't
>know).  On Unibus VAXen, ECC memory is 10 bits/byte; it can *correct*
>single bit errors and detect double bit errors.

Could you either post the details about how VAXen achieve this,
or point out the flaw in the following argument:

With 10 bits you have 2^10 (=1024) different bit patterns.  In order to
encode 8 data bits you need 2^8 (=256) of these to be valid.

Each valid pattern generates a set of 11 patterns, one valid and 10
which are a single bit flip away from the valid pattern.  None of
these 10 can be valid patterns, or a single bit error could go
undetected, let alone uncorrected.  Further, none of them can be
a single bit flip away from some other valid pattern, or you would
have single bit errors which would have two (or more) equally likely
correction paths, thus being uncorrectable.

At this point, however, we need 256*11 (=2816) different patterns,
since there can be no overlap among the 256 sets of 11 patterns.
--
Chuck Goodhart, [e-mail]