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- Newsgroups: comp.arch
- Path: sparky!uunet!ukma!netsys!decwrl!purdue!mentor.cc.purdue.edu!pop.stat.purdue.edu!hrubin
- From: hrubin@pop.stat.purdue.edu (Herman Rubin)
- Subject: Re: Registerless processor
- Message-ID: <Bxo71n.6nI@mentor.cc.purdue.edu>
- Sender: news@mentor.cc.purdue.edu (USENET News)
- Organization: Purdue University Statistics Department
- References: <1992Nov13.181654.11692@fcom.cc.utah.edu>
- Date: Fri, 13 Nov 1992 19:48:57 GMT
- Lines: 28
-
- In article <1992Nov13.181654.11692@fcom.cc.utah.edu> drdavis@u.cc.utah.edu (Darren R. Davis) writes:
- >I have been pondering an idea for a machine architecture. A processor
- >that has no registers.
-
- ............
-
-
- >The one processor I know of is the TI9900 I believe, but it does not
- >have all the cache stuff.
-
- That machine had three registers in the original sense of register, not
- fast memory, the program counter, the condition code register, and the
- register pointer. The register pointer held the address of the 16 word
- block which served as registers currently.
-
- The early von Neumann machines had 3 registers, and some others had only
- the essential one, the program counter. The others in the von Neumann
- machines were the accumulator, where addition/subtraction was actually
- done, and the MQ register, where multipliers were put and quotients
- formed. These were one-address machines; on three-address machines
- of the time, these were generally not present, and those would correspond
- to what you are seeking. There were a fair number of such machines; I
- seem to recall an NCR machine in the 1950's.
- --
- Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
- Phone: (317)494-6054
- hrubin@snap.stat.purdue.edu (Internet, bitnet)
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-