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- Path: sparky!uunet!haven.umd.edu!darwin.sura.net!sgiblab!sgigate!odin!fido!fido!tomw
- From: tomw@orac.asd.sgi.com (Tom Weinstein)
- Newsgroups: comp.arch
- Subject: Re: 600 transistor CPU (was: MINIMUM instruction set)
- Date: 13 Nov 92 02:50:25
- Organization: Silicon Graphics Inc.
- Lines: 25
- Message-ID: <TOMW.92Nov13025025@orac.asd.sgi.com>
- References: <1992Nov10.235849.19192@fcom.cc.utah.edu>
- <1992Nov11.144304.10494@news.uiowa.edu>
- <1992Nov12.164510.28248@dartvax.dartmouth.edu>
- <1992Nov12.220301.23915@fcom.cc.utah.edu>
- Reply-To: tomw@asd.sgi.com
- NNTP-Posting-Host: orac.asd.sgi.com
- In-reply-to: caperkin@ursa11.law.utah.edu's message of Thu, 12 Nov 92 22:03:01 GMT
-
- In article <1992Nov12.220301.23915@fcom.cc.utah.edu>, caperkin@ursa11.law.utah.edu (Charles Perkins) writes:
-
- > Assuming good density, how many of the above could we put on a chip
- > using today's processes (We can make 16 Megabit dram chips... but dram is
- > very regular.)
-
- > How many transistors would it take to make a minimally sized 32-bit chip?
- > Optimized for transistor count, not cycle speed, op-code simplicity, or
- > speed of design.
-
- > This caught my attention because of an idea I have been toying with, which
- > I have decided to call the Fractal Logic Asynchronous Scalable Circuit.
- > (Basically a 'memory' where every cell is a finite state autonoma 'conversing'
- > with the cells next to it.) I figure eight thousand of the little guys on a
- > chip, simple though they might be individually, could get some serious
- > computation done.
-
- Why bother? Why not just make a programmable systolic array processor?
- There's been very little cool stuff done with them in recent years, and
- it seems to me that with the right kind of control logic, you could get
- some rather serious performance.
-
- --
- Love is a conveyor belt of | Tom Weinstein tomw@orac.esd.sgi.com
- warmth -- Jackie Chan | tomw@bears.ucsb.edu
-