NetNews Usenet Archive 1992 #26/NN_1992_26.iso/spool/comp/arch/10537

Internet Message Format | 1992-11-08 | 1.8 KB

Path: sparky!uunet!gatech!prism!emperor!mhopper
From: [e-mail] (Michael A. Hopper)
Newsgroups: comp.arch
Subject: Re: some details on Pentium.
Keywords: RISC Pentium (tm)
Message-ID: <[e-mail]>
Date: 9 Nov 92 04:22:43 GMT
References: <[e-mail]> <[e-mail]> <[e-mail]>
Sender: [e-mail]
Organization: Computer Engineering Research Lab, Georgia Tech.
Lines: 35

In article <[e-mail]> [e-mail] writes:
>There was some recent discussion of how Pentium works.  As it happens, Intel
>

...stuff deleted

>and a couple of read-modify-write thingies.  That's right: x86 is mostly
>load/store.  Of course, it's got variable-length instruction coding, two
>different layers of memory protection, and too, too few registers, so noone
>is ever going to call it a RISC.
>
>To restate: Pentium is organized like a modern RISC, but with a microscopic
>register set, variable-length instructions and a little 'stunt-box' on the
>middle-right to compose complex operations.
>
>regards, Mark

As I understand it, the x86 is NOT ANYWHERE NEAR a load/store architecture.
Load/store means that the data is loaded from memory into a register before
being used in any ALU operations.  The x86 allows all sorts of memory
referencing for most (all?) of its ALU operations.  Examples:

        inc [BX]    ; increment data in memory pointed to by BX.
        add AX [BX]    ; register indirect addressing in ADD op.

Just wanted to clear this up.

-Mike


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