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- Newsgroups: comp.sys.atari.st
- Path: sparky!uunet!mcsun!sunic!aun.uninett.no!nuug!ifi.uio.no!terjeve
- From: terjeve@ifi.uio.no (Terje Vernly)
- Subject: Re: 68040 accelerator board?
- In-Reply-To: baffoni@aludra.usc.edu's message of 7 Sep 1992 22:03:29 -0700
- Message-ID: <TERJEVE.92Sep8123827@ondur.ifi.uio.no>
- Sender: terjeve@ifi.uio.no (Terje Vernly)
- Organization: Dept. of Informatics, University of Oslo, Norway
- References: <9209031931.AA15117@photon.magnus.acs.ohio-state.edu>
- <lafqubINN6fn@aludra.usc.edu> <H.NB0mn1ZPbEM@fredrik.atari.no>
- <laod11INN47r@aludra.usc.edu>
- Date: Tue, 8 Sep 1992 11:38:27 GMT
- Lines: 31
- Originator: terjeve@ondur.ifi.uio.no
-
- In article <laod11INN47r@aludra.usc.edu>, baffoni@aludra.usc.edu (Juxtaposer) writes:
-
- [...some stuff deleted...]
-
- > Hmm. What source are you quoting for the 20mip@25MHz? Motorola?
- > If so, don't forget that they don't take into consideration real-world
- > problems like a) slow internal memory, b) OS overhead/ineffieciency, c)
- > interrupts, etc. Motorola uses an optomised test program (that does nothing
- > but execute no-ops or something similarly useless - maybe it just increments
- z> a counter ... in a register ....) for those figures.
-
- I would guess that the methon they use to find the MIPS-rating of a
- processor is something like this :
-
- Say that you have 4 instructions : A, B, C and D.
- Say that A needs 2 cycles to execute, B needs 3, C needs 4, and D needs 5
- cycles.
- The average instruction would then need (2+3+4+5)/4=3.5 cycles to
- execute. At 25MHz this processor would be able to execute about
- 7.1 Million (average) Instructions Per Second, and would therefor be said to
- yield 7.1 MIPS.
- They don`t just calculate this number by using a NOP as an average
- instruction...
-
- > -Mike
-
- --
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- | Terje Vernly "The dead know only one thing : |
- | InterNet: terjeve@ifi.uio.no It is better to be alive." |
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