NetNews Usenet Archive 1992 #20/NN_1992_20.iso/spool/comp/lsi/testing/217

Internet Message Format | 1992-09-07 | 3.6 KB

Path: sparky!uunet!gatech!hubcap!ncrcae!ncrlnk!ncr-mpd!Don.Allingham
From: [e-mail] (Don Allingham)
Newsgroups: comp.lsi.testing
Subject: Re: To Test or Not to Test?
Message-ID: <[e-mail]>
Date: 3 Sep 92 07:19:39 GMT
References: <[e-mail]>
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In-reply-to: [e-mail]'s message of 28 Aug 92 18:57:18 GMT

In article <[e-mail]> [e-mail] (Janak H. Patel) writes:

>   For high yield (very close to 100%) parts, the answer is very clear,
>   "I hardly ever ship a defective part, so why do I need testing?"
>   In reality, this does happen.  I know two manufactureres who do not
>   test some chips.  These chips are high volume, mature process, and
>   very low cost.  Any testing would just increase the cost. (one also
>   told me that testing would increase defects in such a chip!)

I think a lot of this has to do with the part itself.  Maybe a cheap $1
LCD watch that comes from a typical 100% yield process, this would be
ok.  But for an SRAM for a satellite, I would want to make sure I
completely tested it.  Even 100% yield processes have problems.
Suppliers can ship you bad material.  Machines in the fab may glitch.
There are a lot of variables.

>   Then there are chips with low yield, aggressive design and large number of
>   gates, such as microprocessors, where it is very easy to justify
>   testing and testability benefits.

>   However, a vast majority of ASIC designs fall between these two
>   extremes.  It is here where the situation is very murkey.  It is
>   not very easy to sell testability and high coverage to these group.
>   What if you did only a functional test with 60% coverage?

We normally see a trade off.  The major concerns are:

    1) Time to market
    2) Quality
    3) Cost

Pick any two :-)  Design complexities of ASICs have been skyrocketing in
the past few years.  The many ASICs are starting to become 20k, 30k, and
even 50k+ gates in size.

>   Best case is that,
>   (a) you don't ship very many defective chips. (just lucky!) or,
>   (b) the customers are not very mad at receiving bad chips, or

Boy, would I like to have customers like this :-)  I have some land in
Florida for sale ....

   (c) the customers don't know that it is your chip that is bad in the board
       (they may attribute the defect to the board manufacturing process rather
    than to your chip manufaturing process)

But they will eventually find the problem.  And when they do, you can be
guaranteed a very angry customer.  If for some reason, they don't find
the problem, a low yield may make the board unattractive to manufacture,
and it may be cancelled.  The those selling the chips lose, too.

>   The "best cases" defined above are far from rare, in fact some
>   tell me that it is the norm in their facility.  The "worst cases" are
>   rare at present, but are increasing with the size of the ASICs.

From what I see, the problem is reversed, especially among ASICs.  Maybe
not for DRAMS, SRAMS, or other stable, long term processes.  In the ASIC
market, the processes are always on the leading edge.  You have to be,
or you cannot stay in business.  Everyone wants the leading edge process
because it is denser (cheaper) and faster.  New processes are always
less stable than old, mature processes.

--
Don Allingham
NCR Microelectronics             [e-mail]
Ft. Collins, CO.                uunet!ncrlnk!ncr-mpd!Don.Allingham