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- Newsgroups: comp.lang.verilog
- Path: sparky!uunet!cs.utexas.edu!milano!sirius.mcc.com!praveen
- From: praveen@sirius.mcc.com (Praveen Vishakantaiah)
- Subject: Veritools
- Message-ID: <1992Sep15.140506.7820@mcc.com>
- Sender: news@mcc.com
- Nntp-Posting-Host: sirius.mcc.com
- Organization: Microelectronics and Computer Technology Corp.
- Date: Tue, 15 Sep 1992 14:05:06 GMT
- Lines: 31
-
- I tried to use the veritools that I obtained by doing an "ftp" from
- netcom.netcom.com (this information was posted earlier by someone), but
- got this message:
-
- vflat: "vflat" no such feature configured
-
- Any ideas as to what the problem maybe? Do I need to do something before
- I can starting using the tools.
-
- Also, in the README file in the vflat directory, it says:
-
- Another version of the program, in addition to flattening can also
- translate the netlist from Verilog to several other formats such as
- FutureNet, VHDL, EDIF. IKOS or MOTIVE.
-
- I could not find any such program that can translate netlists in Verilog
- to other HDL. I was particularly interested in translating Verilog
- netlists into VHDL netlists.
-
- Thank you,
- Praveen Vishakantaiah.
-
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- -- Austin, TX 78759. | praveen@mcc.com |
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- -- ALSO A HARD WORKING MEMBER OF :-) |
- -- Computer Engineering Research Center, | Ph : (512)471-8013|
- -- University of Texas, Austin. e-mail : praveen@cerc.utexas.edu |
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