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- Path: sparky!uunet!crdgw1!rdsunx.crd.ge.com!ariel!davidsen
- From: davidsen@ariel.crd.GE.COM (william E Davidsen)
- Newsgroups: comp.arch
- Subject: Re: Multi uP P5 systems
- Message-ID: <1992Sep14.143344.1051@crd.ge.com>
- Date: 14 Sep 92 14:33:44 GMT
- References: <n2vn=9h.erb@netcom.com>
- Sender: usenet@crd.ge.com (Required for NNTP)
- Reply-To: davidsen@crd.ge.com (bill davidsen)
- Organization: GE Corporate R&D Center, Schenectady NY
- Lines: 21
- Nntp-Posting-Host: ariel.crd.ge.com
-
- In article <n2vn=9h.erb@netcom.com>, erb@netcom.com (Elizabeth R. Brown) writes:
- |
- | Well, I'm back. Asia was great. Prepair for hot rumor mongering.
- |
- | On a tour of a major MB manufacturing plant my friend showed me what they
- | were working on in the design lab. It was an EISA board with sockets for
- | four P5 chips! He said the P5 has features that make it very easy to
- | design multi-CPU boards.
-
- I hate to say this, but what is anyone going to plug into the sockets?
-
- Rumor of the day: Intel has dropped the P5 design as unmanufacturable
- and is redesigning the chip in 4000 angstrom biCMOS to improve yeild.
- They will never sell commercial quantities of the P5 as it has been
- shown.
-
- The Intel presentation at FORUM seemed to hint at this, and I've heard
- other things, would someone from Intel care to deny this?
- --
- bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
- I admit that when I was in school I wrote COBOL. But I didn't compile.
-