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- From: mullens@jamsun.ic.ornl.gov (James A. Mullens)
- Subject: Re: Description of Trap Codes
- Message-ID: <1992Aug31.165616.9050@ornl.gov>
- Sender: usenet@ornl.gov (News poster)
- Organization: Oak Ridge National Laboratory
- References: <-13547389@nemesis>
- Date: Mon, 31 Aug 1992 16:56:16 GMT
- Lines: 29
-
- In article <-13547389@nemesis>, uhclem@nemesis.UUCP writes:
- |>
- |> There have been several questions about the various Trap codes
- |> being encountered on the 386/486. Here is a list of the Trap codes,
- |> along with some common causes for each.
- |>
- |> Trap 2 NMI Interrupt
- |> On PC/AT systems, the NMI input to the CPU is usually
- |> connected to the main memory parity circuit. By the time the
- |> error signal is generated, the data may have already been
- |> used in an instruction, so it isn't possible to reliably
- |> recover.
- |>
-
- And some not-so-common causes (from various sources):
-
- PS50+ : I/O channel check, system watch-dog timer time-out interrupt,
- DMA timer time-out interrupt
-
- parity errors on any 8-bit or 16-bit board pulling the IOCHCK* line low,
-
- first generation of auto-switching EGA cards used NMI to trap port
- access for CGA emulation (e.g., ATI's EGA Wonder)
-
- Zeos Notebook low battery (perhaps other battery-based computers)
-
- jim mullens
- jcm@ornl.gov (128.219.128.17) -or- mullens@jamsun.ic.ornl.gov (128.219.64.31)
- voice: 615-574-5564
-