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- Path: sparky!uunet!usc!sol.ctr.columbia.edu!caen!uflorida!usf.edu!sunburn!fevrier
- From: fevrier@sunburn.ec.usf.edu. (Ian Fevrier (EE))
- Newsgroups: comp.sys.ibm.pc.hardware
- Subject: Re: Is a 486-33 with 0 ws cache faster than a 486-50 with 1 ws ?
- Message-ID: <1992Aug22.173032.29468@ariel.ec.usf.edu>
- Date: 22 Aug 92 17:30:32 GMT
- References: <1992Aug16.060405.15165@ariel.ec.usf.edu> <1992Aug21.144712.26345@Warren.MENTORG.COM> <1992Aug22.063339.22929@zeos.com>
- Sender: news@ariel.ec.usf.edu (News Admin)
- Distribution: usa
- Organization: Univ. of South Florida, College of Engineering
- Lines: 31
-
- In article <1992Aug22.063339.22929@zeos.com> kgermann@zeos.com (Ken Germann) writes:
- >In article <1992Aug21.144712.26345@Warren.MENTORG.COM> stu@Warren.MENTORG.COM (Stu Brown) writes:
- >>From article <1992Aug16.060405.15165@ariel.ec.usf.edu>, by fevrier@sunburn.ec.usf.edu. (Ian Fevrier (EE)):
- >>>
- >>>
- >>>
- >>> HELP!!!
- >>>
- >>> The 486-33 cache operated at zero wait state using 25ns
- >>> sram; at 33mhz that works out to 30ns per hit .
- >>>
- >>> On the 486-50 the cache (20ns chips) operates at 1 wait
- >>> state. At 50mhz that's 40ns per hit ??????
- >
- >The clock cycle on the motherboard is probably being split
- >to 25 Mhz before accessing system memory. This would be the result
- >of using a 33 Mhz chip set on the motherboard. Landmark 2.0 and
- >MIPS will show a better processor benchmark than what Norton will.
- >There are significant differences in benchmarks.
- >
- >
- >The speed on the DX-50 needs to be check with multiple benchmarks to
- >get the true speed and feel for what is going on with the particular
- >board design. Norton SI gives an overall system index for performance.
- >When the motherboard clock cycle is being split to 25 mhz to access
- >memory you essentially have a DX2-50 except when you put on a
- >50 Mhz 128k cache.
- >
- >--
- Isn't splitting the clock to 25mhz (40ns) the same as inserting 1 wait
- state ?
-