NetNews Usenet Archive 1992 #19/NN_1992_19.iso/spool/comp/sys/amiga/hardware/14720

Internet Message Format | 1992-08-31 | 3.5 KB

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Newsgroups: comp.sys.amiga.hardware,comp.sys.amiga.introduction
Subject: Re: Question about Accelerators and RAM
Message-ID: <[e-mail]>
From: [e-mail] (LaMonte Koop)
Date: 31 Aug 92 11:03:04 -0600
Reply-To: [e-mail]
References: <[e-mail]>
Distribution: usa
Organization: St. Cloud State University, St. Cloud, MN
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In article <[e-mail]>, [e-mail] (Michael A. Kopack) writes:
>Got a question for you all.
>
>I recently purchased a Supra RAM board with 2 Megs of 16 bit RAM for my A2000.
>I now have the opportunity to get my hands on an accelerator board (68020),
>knowing that I can use the 16 bit ram but slowing down the speed increase.
>
>My question is: If I buy this accelerator, Add 32 bit ram to it, will the
>system access both the 32 and 16 bit RAM together?? I already have 3 MEGS,
>and the board I'm considering has 2 built it. Would I end up with 5 Megs
>of accessable RAM????

    Yes, there is no problem with this setup.  The primary difference between
"16 bit" and "32 bit" RAM, as it has been called, is the data path between
the RAM and the processor, and not any obscure strangeness on the part of
the actual RAM.  The accelerator will simply handle things differently when
accessing the 32 bit ported RAM, as opposed to the RAM on the 16-bit bus
characteristic on the A2000 (in the former case, the RAM will simply be
accessed at the speed of the 020, using a full 32-bit data path, while
in the latter case, some extra ju-ju is used to emulate 68000 bus cycles
on the motherboard using a 16-bit data path and at the motherboard clock
rate).
    Putting aside the differences in the accelerator clock rate, and the
motherboard, you could even have 16-bit ported RAM (or even 8-bit) on the
accelerator if someone had designed it this way (though this is not
efficiency-wise), as the 68020 and 68030 utilize a dynamic bus sizing
mechanism to determine and act accordingly to different RAM port sizes.
    In general, with a setup such as yours, you will end up with three regions
of memory; your CHIP ram, your 16-bit FAST RAM, and the 32-bit ported RAM
on the accelerator.  Each of these regions will have a different address range,
and the way the accelerator treats them will be dependent on this range.  For
accesses which fall within the range of the memory contained on the accelerator,
normal 68020 bus cycles will be run to that RAM, and it will respond according
to the specifications of such.  Accesses to your 16-bit resources (CHIP RAM,
and 16-bit FAST RAM) will appear to said resources as standard 68000 bus
cycles, as the accelerator will emulate such to make the accesses.  The
transfers will be slower than with a 32-bit port running at the same clock as
the processor, and only 16-bit quantities can be transferred at once, but
should be transparent to the system otherwise.

                 ----------------------------------------
           LaMonte Koop -- SCSU Electrical/Computer Engineering
 Internet: [e-mail] -OR- [e-mail]
              "You mean you want MORE lights on this thing???"
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