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- Newsgroups: comp.os.os2.misc
- Path: sparky!uunet!stanford.edu!agate!linus!linus.mitre.org!agriffin
- From: agriffin@mitre.org (James Artcher Griffin)
- Subject: Re: OS2 WINS!! I give up!
- Message-ID: <agriffin.714919008@tsfsrv>
- Sender: news@linus.mitre.org (News Service)
- Nntp-Posting-Host: tsfsrv.mitre.org
- Organization: The MITRE Corporation
- References: <26AUG199210035893@lims01.lerc.nasa.gov> <1992Aug26.200451.13762@njitgw.njit.edu> <1992Aug27.015416.6882@maccs.dcss.mcmaster.ca>
- Distribution: all
- Date: Thu, 27 Aug 1992 12:36:48 GMT
- Lines: 27
-
- In <1992Aug27.015416.6882@maccs.dcss.mcmaster.ca> riehm@maccs.dcss.mcmaster.ca (Carl Riehm) writes:
-
- >>In article <26AUG199210035893@lims01.lerc.nasa.gov> solomon@lims01.lerc.nasa.gov (Robert F. Solomon) writes:
-
- >a horrible tale of woe... I'm just about to install OS/2, but after reading
- >his experience, I very worried. I *do* have a mixture of memory (on my IBM
- >Model 70) which is certainly from different manufacturers, and almost certainly
- >different speeds. Does anyone else have any experience with using differing
- >memory simms with OS/2? When IBM itself warns against this situation,
- >it sounds serious! Carl Riehm.
-
- As others have written, "Your mileage may vary." My nameless 486/25MHz
- 128KCache 16MB motherboard has a mix of 70ns and 80ns made up of nine
- and three chip SIMMs. When I was only running DOS and MSWin 3.0, I
- could setup for zero waitstate. With OS/2 making full use the the
- addressing capabilities of the 386/486 processor, timing is more
- critical and I had to set the board for one-waitstate on both read and
- write.
-
- Along the same line (critical timing issues), I had to return the ISA
- bus clock to its design setting of 8MHz for the system to run reliably.
-
- Others have reported the same experience. So, Robert and Carl, if you
- have been "pushing" your motherboard reduce your speed a little and join
- the productivity enhancing world of OS/2 2.0. (Hopefully) HTH
-
- Artch
-