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- From: todd@vulcan.austin.ibm.com (Todd Clayton)
- Newsgroups: comp.arch
- Subject: ADVANCE PROGRAM for ASPLOS V
- Message-ID: <1992Aug25.200943.9177@awdprime.austin.ibm.com>
- Date: 25 Aug 92 20:09:43 GMT
- Sender: news@awdprime.austin.ibm.com (USENET News)
- Organization: IBM PSP Austin, Tx.
- Lines: 383
-
- I am posting this for Steve White.
-
-
- ADVANCE PROGRAM
- Fifth International Conference
- on Architectural Support for
- Programming Languages
- and Operating Systems
-
- October 12-15, 1992
- Boston, Massachusetts
-
- SIGARCH Sponsored by the ACM TC MM
- SIGPLAN in cooperation with the TC VLSI
- SIGOPS IEEE Computer Society TC OS
-
- *****************************************************
- *****************************************************
- ** **
- ** Register early for a free ASPLOS T-shirt. **
- ** **
- *****************************************************
- *****************************************************
-
- Monday, October 12
- ==================
- Tutorial I:
- High-Performance Shared Memory: Implementation Issues and
- Consistency Models,
- Sarita V. Adve and Mark D. Hill, Unviersity of Wisconsin-Madison
-
- Implementation options for high-performance shared-memory will
- be surveyed, including program sharing patterns (e.g., read-mostly
- and migratory), reducing memory latency with cache coherence
- (e.g., by snooping, directories or software), tolerating memory la-
- tencies with prefetching or multiple contexts. Hardware shared
- memory systems will be contrasted with shared virtual memory sys-
- tems. Theoretical and practical issues regarding memory consis-
- tency models will be explored, including the performance potential
- and ease-of-use aspects of sequential consistency and several
- weaker models (e.g., processor consistency, weak ordering, release
- consistency, and SPARC's TSO and PSO).
-
- Tutorial II:
- Instruction-Level Parallel Processing: Superscalar Processor Design,
- John Paul Shen, Carnegie Mellon University
-
- This tutorial presents the hardware and software techniques for su-
- perscalar processor design. Topics covered include: superpipelined,
- superscalar, supersymmetric and VLIW machines; limits of instruc-
- tion-level parallelism (ILP); dynamic techniques for detecting and
- resolving data and control dependencies (e.g. scoreboarding, register
- renaming, load bypassing and forwarding, branch prediction, and
- out-of-order/speculative execution); static techniques for depen-
- dency resolution (e.g. instruction boosting, and instruction schedul-
- ing for predicated/speculative execution); and recent quantitative
- experimental results on limits of these techniques for future super-
- scalars. We will survey current superscalar designs, including:
- R4000, RS/6000, Supersparc, PA-RISC 7100, i960CA and Alpha;
- detailed instruction-level evaluation of the IBM RS/6000 and
- Multiflow TRACE/300.
-
- Monday, October 12
- ASPLOS-V Reception : An informal gathering for conference and tutorial
- attendees.
-
- Tuesday October 13
- ==================
- Welcome and Keynote Address, Butler Lampson, DEC
- Cambridge Research Lab
-
- Session I: File Systems, Chair: Randy Katz
-
- On-line Data Compression in a Log-structured File System, Michael
- Burrows, Charles Jerian, Butler Lampson, and Timothy Mann
- (DEC System Research Center).
-
- Non-volatile Memory for Fast, Reliable File Systems. Mary Baker,
- Satoshi Asami, Etienne Deprit, John Ousterhout and Margo Seltzer
- (Univ. of California, Berkeley).
-
- Parity Declustering for Continuous Operation in Redundant Disk
- Arrays. Mark Holland and Garth A. Gibson (Carnegie Mellon).
-
- Session II: Software and Hardware for Prefetching, Chair: David
- Callahan
-
- Software Support for Speculative Loads. Anne Rogers and Kai Li
- (Princeton University).
-
- Reducing Memory Latency via Non-blocking and Prefetching
- Caches. Tien-Fu Chen and Jean-Loup Baer (Univ. of Washington).
-
- Design and Evaluation of a Compiler Algorithm for Prefetching.
- Todd C. Mowry, Monica S. Lam and Anoop Gupta (Stanford
- University).
-
- Session III: Branch Prediction, Chair: Thomas Gross
-
- Improving the Accuracy of Dynamic Branch Prediction Using
- Branch Correlation. Shien-Tai Pan and Kimming So (IBM), and
- Joseph T. Rahmeh (Univ. of Texas, Austin).
-
- Predicting Conditional Branch Directions from Previous Runs
- of a Program. Joseph A. Fisher and Stefan M. Freudenberger
- (Hewlett-Packard Labs).
-
- Session IV: Networks and Communications, Chair: Anant Agarwal
-
- High Speed Switch Scheduling for Local Area Networks. Thomas
- E. Anderson (Univ. of California, Berkeley), and Susan S. Owicki,
- James B. Saxe, and Charles P. Thacker (DEC System Research Center).
-
- A Tightly-Coupled Processor-Network Interface.
- Dana S. Henry and Christopher F. Joerg (MIT).
-
- Evening Panel Session and Open Bar
-
- Wednesday October 14
- ====================
- Session V: Caches and Memory Management, Chair: Douglas Clark
-
- Consistency Management for Virtually Indexed Caches.
- Bob Wheeler and Brian N. Bershad (Carnegie Mellon).
-
- Eliminating the Address Translation Bottleneck for Physical
- Address Cache. Tzi-cker Chiueh and Randy H. Katz
- (Univ. of California, Berkeley).
-
- A Performance Evaluation of Optimal Hybrid Cache Coherency
- Protocols. Jack E. Veenstra and Robert J. Fowler (Univ. of
- Rochester).
-
- Session VI: Architecture and Operating Systems, Chair: John Wilkes
-
- Characterizing the Caching and Synchronization Performance of a
- Multiprocessor Operating System. Josep Torrellas, Anoop Gupta
- and John Hennessy (Stanford).
-
- Architectural Support for Single Address Space Operating Systems.
- Eric J. Koldinger, Jeffrey S. Chase, and Susan J. Eggers (Univ. of
- Washington).
-
- Application-Controlled Physical Memory using External Page-
- Cache Management, Kieran Harty and David R. Cheriton (Stanford).
-
- Session VII Miscellaneous Topics, Chair: Anita Borg
-
- Efficient Data Breakpoints. Robert Wahbe (Univ. of California,
- Berkeley).
-
- Migrating a CISC Computer Family onto RISC via Object Code
- Translation. Kristy Andrews and Duane Sand (Tandem Com-
- puter Corporation).
-
- Fast Mutual Exclusion for Uniprocessors. Brian N. Bershad
- (Carnegie Mellon), and David D. Redell and John R. Ellis (DEC
- System Research Center).
-
- Session VIII: Work in Progress Session, Chair: Susan Eggers
-
- [see detail below]
-
- Evening Panel Session and Open Bar
-
- Thursday October 15
- ===================
- Session IX: Superscalars, Chair: Mary Lou Soffa
-
- Sentinel Scheduling for VLIW and Superscalar Processors. Scott A.
- Mahlke, William Y. Chen, and Wen-mei W. Hwu (Univ. of Illi-
- nois), and B. Ramakrishna Rau and Michael S. Schlansker
- (Hewlett-Packard Labs).
-
- Efficient Superscalar Performance Through Boosting. Michael D.
- Smith, Mark Horowitz, and Monica S. Lam (Stanford).
-
- Session X: Multiprocessors: Hardware and Software, Chair: David Cheriton
-
- Cooperative Shared Memory: Software and Hardware Support for
- Scalable Multiprocessors. Mark D. Hill, James R. Larus, Steven
- K. Reinhardt, and David A. Wood (Univ. of Wisconsin).
-
- Closing the Window of Vulnerability in Multiphase Memory Trans-
- actions. John Kubiatowicz, David Chaiken, and Anant Agarwal
- (MIT).
-
- Access Normalization: Loop Restructuring for NUMA Compilers.
- Wei Li and Keshav Pingali (Cornell University).
-
- Work in Progress Session
-
- This year ASPLOS will feature a "work in progress" session,
- consisting of 5-minute presentations on ASPLOS-oriented work in
- progress, or even opinions about technical (and certainly controver-
- sial) topics. If you are interested in participating, please send an ab-
- stract of no more than one page to Susan Eggers, preferably through
- email (eggers@cs.washington.edu) or at Dept. of Computer Science
- and Engineering, Univ. of Washington, Seattle, WA 98195. Your
- abstract must be received by September 15, 1992; final notification
- will be just prior to the conference.
-
- As is customary for ASPLOS, there will be panel sessions in
- the evenings on controversial and/or topical subjects. This year there
- will be a reception on Monday evening and panels on both Tuesday
- and Wednesday evenings. An open bar will be available during both
- panel sessions.
-
- Conference Chairs
-
- General Barry Flahive, Hewlett-Packard
- Program Hank Levy, University of Washington
- Treasurer Bob Nix, Digital Equipment Corporation
- Publicity Jeanette McWilliams, IBM
- Steven White, IBM
- Local Arrangements David Levine, Hewlett-Packard
- Registration Hugh Lauer, Mitsubishi Electric Research
- Tutorials Bruce Olsen, Hewlett-Packard
-
- Program Committee
-
- Hank Levy University of Washington (chair)
- Anant Agarwal MIT
- Anita Borg DEC Western Research Lab
- David Callahan Tera Computer Corporation
- David Cheriton Stanford University
- Doug Clark Digital Equipment Corporation
- David Ditzel Sun Microsystems
- Susan Eggers University of Washington
- Thomas Gross Carnegie Mellon University
- Randy Katz Univ. of California, Berkeley
- David May INMOS Limited
- Mary Lou Soffa University of Pittsburgh
- Guy Steele Thinking Machines Corporation
- John Wilkes Hewlett-Packard Laboratories
-
- Registration
-
- Conference registration includes one copy of the proceed-
- ings, lunches, breaks, banquet, and receptions. Registration for
- tutorial sessions includes both tutorials plus one copy of notes
- for each tutorial, a lunch, and breaks. The student registration fee
- excludes meals; however by tradition, regular ASPLOS attendees who do
- not plan to use their meal tickets normally donate them to students.
- Electronic mail or fax registration requires payment by credit
- card. A registration form may be retrieved by anonymous ftp from
- merl.com, file /asplos/registration.form. (One is also included at
- the end of this file.) For further information, contact Darlene
- Forsyth at (508) 436-5450 or asplos@apollo.hp.com.
-
-
- Transportation
-
- Boston's Logan Airport is located very near downtown and
- the Park Plaza Hotel. Airways Transportation operates a shuttle
- from the airport every half hour to all downtown hotels; fare is
- $7.50. A taxi cab costs about $12-15 and takes 20-40 min-
- utes. The fastest way from the airport is via MBTA subway.
- Take the free shuttle bus to Airport Station, then take the Blue
- Line inbound to Government Center, change to the Green Line, and
- go to the Arlington station. The hotel is one block south of
- Arlington Station, and three blocks from the Amtrak Back Bay Station.
- Through special arrangements with Continental Airlines, conference
- attendees will be eligible for the lowest rate round-trip fare
- without having to stay over Saturday night. This represents a 50%
- savings over the normal fare available to most people. (Other
- restrictions, such as advance purchase, restrictions on changes, etc.,
- still apply; only the Saturday night stay is waived.) In addition,
- other discounted airline fares are available. To take
- advantage of this offer, please contact Colpitts Travel of
- Lexington, Massachussetts, at (800)441-4023, and mention "ASPLOS".
-
-
- Climate
-
- Weather in Boston in October ranges from chilly to warm.
- Early morning temperatures may be as low as 35 F, but tem-
- peratures may rise to the upper 70s F during the day. A jacket
- will probably be needed, and rain is always a possiblity. Casual
- attire is appropriate throughout the conference.
-
-
- Conference Site and Accomodation
-
- All technical sessions, lunches, and registration will be held
- at the Boston Park Plaza Hotel and Towers.
- Contact the hotel directly for reservations and indicate ASPLOS-V
- Conference. Conference rates are $105 for single and $115 for double,
- (9.7% State and City tax not included). Reservations must be received
- by September 14, 1992, to guarantee conference rate. Late reservations
- accepted on a space-available basis.
-
- Boston Park Plaza Hotel
- 64 Arlington Street
- Boston, MA 02117
- (617) 426-2000; Fax: (617) 426-5545
-
-
- ASPLOS-V Registration Form
-
- ASPLOS-V
- P.O. Box 1455
- Concord, MA 01742
- (617) 621-7503; Fax: (617) 621-7550
- Attention: Hugh Lauer
-
- e-mail To: asplos@apollo.hp.com
- Cc:
- Subject: Registration for ASPLOS-5 Conference
-
- For further information, contact Darlene Forsyth at (508) 436-5450 or
- asplos@apollo.hp.com.
-
-
- REGISTRATION:-
-
-
- Name: ________________________________________________________________
-
- Affiliation: _________________________________________________________
-
- Address: _____________________________________________________________
-
-
- Daytime telephone: ___________________________________________________
-
- ACM Member # ___________________ or IEEE Member # ____________________
-
- Electronic mail address:
-
- Please list any special needs or accommodations
-
-
-
- FEES:-
-
- (Before Sept 14) Member Non-member Student
-
- Symposium $295 ___ $413 ___ $120 ___
- Tutorial $205 ___ $287 ___ $97 ___
-
- T-Shirt Size Small ___ Medium ___ Large ___ X-Large ___
- (T-shirt included only with paid registrations
- received by Sept 14)
-
- (After Sept 14) Member Non-member Student
-
- Symposium $398 ___ $558 ___ $120 ___
- Tutorial $277 ___ $387 ___ $97 ___
-
- Student registration must be able to produce a valid, full-time
- student ID; meals not included in student registration.
-
- PAYMENT:-
-
- Check drawn on U.S. bank payable to : ASPLOS-V ____
-
- MasterCard ___ Visa ___
-
- Card no.: _____________________________________________
-
- Expiration date: ______________________________________
-
- Name on card: _________________________________________
-
- Signature: ____________________________________________
-
-
-
- *****************************************************
- *****************************************************
- ** **
- ** Register early for a free ASPLOS T-shirt. **
- ** **
- *****************************************************
- *****************************************************
-
-
- --
- "My opinions above, facts below."
- Todd Clayton, AIX Performance IBM Austin, Tx.
- INTERNET work: todd@perfmap.austin.ibm.com
- Phone work: (512) 838-7905
-