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- From: davidsen@ariel.crd.GE.COM (william E Davidsen)
- Newsgroups: comp.arch
- Subject: Re: CACHE MISS PENALTY FOR 386/486??
- Message-ID: <1992Aug19.173640.19011@crd.ge.com>
- Date: 19 Aug 92 17:36:40 GMT
- References: <1992Aug19.042318.10163@nuscc.nus.sg> <PCG.92Aug19114950@aberdb.aber.ac.uk>
- Sender: usenet@crd.ge.com (Required for NNTP)
- Reply-To: davidsen@crd.ge.com (bill davidsen)
- Organization: GE Corporate R&D Center, Schenectady NY
- Lines: 14
- Nntp-Posting-Host: ariel.crd.ge.com
-
- In article <PCG.92Aug19114950@aberdb.aber.ac.uk>, pcg@aber.ac.uk (Piercarlo Grandi) writes:
-
- | Probably you are assuming a bit too much. I have seen dozens of types of
- | AT style systems, and none was 'typical'. Actually I doubt that a
- | 'typical' AT style system exists.
-
- Most of the decent 486 board seem to have either Nx9 SIMMs in groups
- of four, usually with no interleave even if you have two banks, or Nx36
- SIMMs with or without interleave. Interestingly some of the cheap boards
- have 2 and 4 way if you populate them.
-
- --
- bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
- I admit that when I was in school I wrote COBOL. But I didn't compile.
-