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- From: pcg@aber.ac.uk (Piercarlo Grandi)
- Newsgroups: comp.arch
- Subject: Re: CACHE MISS PENALTY FOR 386/486??
- Message-ID: <PCG.92Aug19114950@aberdb.aber.ac.uk>
- Date: 19 Aug 92 11:49:50 GMT
- References: <1992Aug19.042318.10163@nuscc.nus.sg>
- Sender: news@aber.ac.uk (USENET news service)
- Reply-To: pcg@aber.ac.uk (Piercarlo Grandi)
- Organization: Prifysgol Cymru, Aberystwyth
- Lines: 30
- In-Reply-To: eletanjm@nuscc.nus.sg's message of 19 Aug 92 04: 23:18 GMT
- Nntp-Posting-Host: aberdb
-
- On 19 Aug 92 04:23:18 GMT, eletanjm@nuscc.nus.sg (TAN JIN MENG) said:
-
- eletanjm> Just what is a typical cache miss penalty on (1) a 386 system
- eletanjm> with external cache (2) a 486 system with only internal cache
- eletanjm> (3) a 486 system with internal cache and external secondary
- eletanjm> cache
-
- I think it is about something percent. :-)
-
- More seriously, the cache miss penalty depends on several parameters,
- just like memory accesses, including for example how the memory is
- organized, the bus transactions used to access memory, and so on. The
- range of variation is quite large. In some boards the way the memory
- works depends on how much memory you put in, for example.
-
- eletanjm> I'm assuming an typical AT style system.
-
- Probably you are assuming a bit too much. I have seen dozens of types of
- AT style systems, and none was 'typical'. Actually I doubt that a
- 'typical' AT style system exists.
-
- eletanjm> Just how do you determine the miss penalty anyway?
-
- You ask the designer of the board, if s/he has got any clue (which may
- or may not be the case), or you use a suitable analyzer (a fast storage
- oscilloscope may be enough) hooked to the relevant pins.
- --
- Piercarlo Grandi | JNET: pcg@uk.ac.aber
- Dept of CS, University of Wales | UUCP: ...!mcsun!ukc!aber-cs!pcg
- Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@aber.ac.uk
-