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PALASM Design Description  |  1991-02-27  |  5.4 KB  |  182 lines
  1. ;PALASM Design Description
  2.  
  3. ;---------------------------------- Declaration Segment ------------
  4. TITLE    load internal registers
  5. PATTERN  
  6. REVISION 
  7. AUTHOR   john davis
  8. COMPANY  SIVAD for AMD
  9. DATE     12/07/90
  10.  
  11. CHIP  _la_rload  MACH210
  12. ;---------------------------------- PIN Declarations ---------------
  13. PIN  ?  /POR    COMBINATORIAL            ; Power On Reset
  14. NODE 1 POR_INIT
  15. PIN  35 CLK1                            ; Default Clock on pin 35
  16. PIN  ?  K_CLK COMBINATORIAL             ; 
  17.  
  18. PIN  ?  GO
  19. PIN  ?  LOAD
  20. PIN  ?  /CLR_SR
  21. PIN  ?  /HOLD
  22. PIN  ?  MSW[0] REGISTERED                 ; 
  23. PIN  ?  MSW[1] REGISTERED                 ; 
  24. PIN  ?  MSW[2] REGISTERED                 ; 
  25. PIN  ?  MSW[3] REGISTERED                 ; 
  26. PIN  ?  MSW[4] REGISTERED                 ; 
  27. PIN  ?  MSW[5] REGISTERED                 ; 
  28. PIN  ?  MSW[6] REGISTERED                 ; 
  29. PIN  ?  MSW[7] REGISTERED                 ; 
  30. PIN  ?  MSW[8] REGISTERED                 ; 
  31. PIN  ?  MSW[9] REGISTERED                 ; 
  32. PIN  ?  MSW[10] REGISTERED                ; 
  33. PIN  ?  MSW[11] REGISTERED                ; 
  34. PIN  ?  MSW[13] REGISTERED                ; 
  35. PIN  ?  MSW[14] REGISTERED                ; 
  36. PIN  ?  MSW[15] REGISTERED                ; 
  37.  
  38. PIN  ?  REQ        REGISTERED                ; 
  39. PIN  ?  RPL        REGISTERED                ; 
  40. PIN  ?  INP3
  41. PIN  ?  INP2
  42. PIN  ?  INP1
  43. PIN  ?  INP0
  44.  
  45. ;************ BURIED REGISTERS ********************
  46. NODE ?  K0 REGISTERED                     ;
  47. NODE ?  K1 REGISTERED                     ; 
  48. NODE ?  K2 REGISTERED                     ; 
  49. NODE ?  K3 REGISTERED                     ; 
  50. NODE ?  SR0 REGISTERED                    ;Internal timing shift register
  51. NODE ?  SR1 REGISTERED                    ;Internal timing shift register
  52. NODE ?  SR2 REGISTERED                    ;Internal timing shift register
  53. NODE ?  SR3 REGISTERED                    ;Internal timing shift register
  54. NODE ?  SR4 REGISTERED                    ;Internal timing shift register
  55. NODE ?  SR5 REGISTERED                    ;Internal timing shift register
  56. NODE ?  SR6 REGISTERED                    ;Internal timing shift register
  57. NODE ?  SR7 REGISTERED                    ;Internal timing shift register
  58. NODE ?  SR8 REGISTERED                    ;Internal timing shift register
  59. ;       
  60. ;STRING DECLARATIONS.
  61. STRING GL '(MSW[0])'
  62. STRING DL '(MSW[1])'
  63. STRING BF '(MSW[2])'
  64. STRING TR0 'MSW[3]'
  65. STRING TR1 'MSW[4]'
  66. STRING TR2 'MSW[5]'
  67. STRING ST '(MSW[6])'
  68. STRING XCK '(MSW[7])'
  69. STRING TG '(MSW[8])'
  70. STRING SM '(MSW[9])'
  71. STRING XS '(MSW[10])'                ;External Sync Input
  72. STRING CS '(MSW[11])'
  73. STRING EQ '(MSW[12])'
  74. STRING TA '(MSW[13)'
  75. STRING TD '(MSW[14])'
  76. STRING RUN '(MSW[15])'
  77.  
  78.  
  79. STRING S_K0  '/POR*/K3*/K2*/K1*/K0'        ;Main Control State Bits
  80. STRING S_K1  '/POR*/K3*/K2*/K1* K0'
  81. STRING S_K2  '/POR*/K3*/K2* K1*/K0'
  82. STRING S_K3  '/POR*/K3*/K2* K1* K0'
  83. STRING S_K4  '/POR*/K3* K2*/K1*/K0'
  84. STRING S_K5  '/POR*/K3* K2*/K1* K0'
  85. STRING S_K6  '/POR*/K3* K2* K1*/K0'
  86. STRING S_K7  '/POR*/K3* K2* K1* K0'
  87. STRING S_K8  '/POR* K3* K2*/K1*/K0'
  88.  
  89. STRING S_K_C5_4  ' K_C5_4'
  90. STRING S_LOAD '/POR*LOAD'
  91. STRING SHIFT 'HOLD'
  92. STRING S_R0  'SR0'
  93.  
  94.  
  95. STRING S_TDD    '/TR2*/TR1*/TR0'        ;Operational Mode Bits
  96. STRING S_TTD    '/TR2*/TR1* TR0'
  97. STRING S_TAD    '/TR2* TR1*/TR0'
  98. STRING S_TBD     '/TR2* TR1* TR0'
  99. STRING S_LD_RG     ' TR2*/TR1*/TR0'
  100. STRING S_LD_AT     ' TR2*/TR1* TR0'
  101. STRING S_LSA     '(S_TDD+S_TTD+S_TAD+S_TBD)'
  102. STRING S_SET     '(S_LD_RG+S_LD_AT)'
  103. ;------------------- Boolean Equation Segment ------
  104. EQUATIONS
  105.  
  106. ;------------ Initialization 
  107. POR_INIT.RSTF= POR
  108. ;------------ Operation
  109.  
  110. SR8 =  /CLR_SR*SHIFT*SR7+/CLR_SR*/HOLD*SR8
  111. SR7 =  /CLR_SR*SHIFT*SR6+/CLR_SR*/HOLD*SR7
  112. SR6 =  /CLR_SR*SHIFT*SR5+/CLR_SR*/HOLD*SR6
  113. SR5 =  /CLR_SR*SHIFT*SR4+/CLR_SR*/HOLD*SR5
  114. SR4 =  /CLR_SR*SHIFT*SR3+/CLR_SR*/HOLD*SR4
  115. SR3 =  /CLR_SR*SHIFT*SR2+/CLR_SR*/HOLD*SR3
  116. SR2 =  /CLR_SR*SHIFT*SR1+/CLR_SR*/HOLD*SR3
  117. SR1 =  /CLR_SR*SHIFT*SR0+/CLR_SR*/HOLD*SR1
  118. SR0 =  /CLR_SR*LOAD*SHIFT*(S_K3+S_K4)
  119. ;      +/CLR_SR*LOAD*SHIFT*SR0
  120. ;      +/CLR_SR*LOAD*/HOLD*SR0
  121. ;---------------------------State Machine -----------------------------
  122. STATE
  123.  
  124. M_C5_0  = /K3*/K2*/K1*/K0                 ;Main Control State Definition
  125. M_C5_1  = /K3*/K2*/K1* K0
  126. M_C5_2  = /K3*/K2* K1*/K0
  127. M_C5_3  = /K3*/K2* K1* K0
  128. M_C5_4  = /K3* K2*/K1*/K0
  129. M_C5_5  = /K3* K2*/K1* K0
  130. M_C5_6  = /K3* K2* K1*/K0
  131. M_C5_7  = /K3* K2* K1* K0
  132. M_C5_8  =  K3*/K2*/K1*/K0
  133.  
  134.  
  135. MEALY_MACHINE            ;Main  Trace Control State Machine
  136.  
  137. M_C5_0 := START -> M_C5_1
  138.                 +-> M_C5_0;
  139.  
  140. M_C5_1 := VCC -> M_C5_2
  141.                 +-> M_C5_1;
  142.  
  143. M_C5_2 := T_LOAD -> M_C5_3
  144.                 +-> M_C5_2;
  145.  
  146. M_C5_3 := T_ZERO -> M_C5_7
  147.         + N_ZERO ->M_C5_4
  148.                 +-> M_C5_0;
  149.  
  150. M_C5_4 := T_SR8 -> M_C5_5
  151.         + N_SR8 -> M_C5_3
  152.                 +-> M_C5_0;
  153.  
  154. M_C5_5 := VCC -> M_C5_6
  155.                 +-> M_C5_0;
  156.  
  157. M_C5_6 := VCC -> M_C5_0
  158.                 +-> M_C5_0;
  159.  
  160. M_C5_7 := VCC  -> M_C5_8
  161.                 +-> M_C5_0;
  162.  
  163. M_C5_8 := N_SR8 -> M_C5_7
  164.         + T_SR8 -> M_C5_0
  165.                 +-> M_C5_0;
  166.  
  167. ;-----------------------Outputs--------------------------
  168. ;-----------------------Conditions-----------------------
  169. CONDITIONS
  170. START = /POR*GO*S_LD_RG
  171. T_LOAD = /POR*LOAD*S_LD_RG
  172. T_ZERO = /POR* /INP3*/INP2*/INP1*/INP0*S_LD_RG
  173. N_ZERO = /POR*( INP3+ INP2+ INP1+ INP1)*S_LD_RG
  174.  
  175. T_SR8 = /POR*LOAD* SR8*S_LD_RG
  176. N_SR8 = /POR*LOAD*/SR8*S_LD_RG
  177. ;--------------------------OUTPUTS----------------------------------
  178. ;------------------------- Simulation Segment ----------------------
  179.  
  180.  
  181.  
  182.