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PALASM Design Description  |  1991-02-27  |  3.6 KB  |  120 lines
  1. ;PALASM Design Description
  2.  
  3. ;---------------------------------- Declaration Segment ------------
  4. TITLE    
  5. PATTERN  
  6. REVISION 
  7. AUTHOR   john davis
  8. COMPANY  SIVAD for AMD
  9. DATE     01/29/91
  10.  
  11. CHIP  _la_comb2  MACH110
  12. ;-------------------------------------------------------------------
  13. ;---------------------------------- PIN Declarations ---------------
  14. PIN  ?  /POR    COMBINATORIAL            ; Power On Reset
  15. NODE 1 POR_INIT
  16. PIN  35 CLK1                            ; Default Clock on pin 35
  17. PIN  ?  K_CLK COMBINATORIAL             ; 
  18.  
  19. PIN  ?  MSW[3] REGISTERED                 ; 
  20. PIN  ?  MSW[4] REGISTERED                 ; 
  21. PIN  ?  MSW[5] REGISTERED                 ; 
  22. PIN  ?  MSW[15] REGISTERED                ; 
  23.  
  24. PIN ?  K0 REGISTERED                   ; 
  25. PIN ?  K1 REGISTERED                   ; 
  26. PIN ?  K2 REGISTERED                   ; 
  27. PIN ?  K3 REGISTERED                   ; 
  28. PIN  ?  /TM_G_CS    COMBINATORIAL              ; global chip select
  29. PIN  ?  /TM_G_OE    COMBINATORIAL              ; global output select
  30. PIN  ?  /TM_G_WE       COMBINATORIAL              ; global write enable
  31. PIN  ?   TM_G_ADDR_CK  COMBINATORIAL          ; Address Clock 
  32. PIN  ?  /GM_G_CS    COMBINATORIAL              ; global chip select
  33. PIN  ?  /GM_G_OE    COMBINATORIAL              ; global output select
  34. PIN  ?  /GM_G_WE       COMBINATORIAL              ; global write enable
  35. PIN  ?   GM_G_ADDR_CK  COMBINATORIAL          ; Address Clock 
  36. NODE ?  K_C0_0 REGISTERED                 ; 
  37. NODE ?  K_C0_1 REGISTERED                 ; 
  38. NODE ?  K_C1   REGISTERED                 ; 
  39. NODE ?  K_C2_0 REGISTERED                 ; 
  40. NODE ?  K_C2_1 REGISTERED                 ; 
  41. NODE ?  K_C3 REGISTERED                   ; 
  42. NODE ?  K_C4 REGISTERED                   ; 
  43.  
  44. ;STRING DECLARATIONS.
  45. STRING GL '(MSW[0])'
  46. STRING DL '(MSW[1])'
  47. STRING BF '(MSW[2])'
  48. STRING TR0 'MSW[3]'
  49. STRING TR1 'MSW[4]'
  50. STRING TR2 'MSW[5]'
  51. STRING ST '(MSW[6])'
  52. STRING XCK '(MSW[7])'
  53. STRING TG '(MSW[8])'
  54. STRING SM '(MSW[9])'
  55. STRING XS '(MSW[10])'
  56. STRING CS '(MSW[11])'
  57. STRING EQ '(MSW[12])'
  58. STRING TA '(MSW[13])'
  59. STRING TD '(MSW[14])'
  60.  
  61. STRING S_K0  '/K3*/K2*/K1*/K0'        ;Main Control State Bits
  62. STRING S_K1  '/K3*/K2*/K1* K0'
  63. STRING S_K2  '/K3*/K2* K1*/K0'
  64. STRING S_K3  '/K3*/K2* K1* K0'
  65. STRING S_K4  '/K3* K2*/K1*/K0'
  66. STRING S_K5  '/K3* K2*/K1* K0'
  67. STRING S_K6  '/K3* K2* K1*/K0'
  68. STRING S_K7  '/K3* K2* K1* K0'
  69. STRING S_K8  ' K3*/K2*/K1*/K0'
  70.  
  71. STRING S_TDD    '/TR2*/TR1*/TR0'        ;Operational Mode Bits
  72. STRING S_TTD    '/TR2*/TR1* TR0'
  73. STRING S_TAD    '/TR2* TR1*/TR0'
  74. STRING S_TBD     '/TR2* TR1* TR0'
  75. STRING S_LD_RG     ' TR2*/TR1*/TR0'
  76. STRING S_LD_AT     ' TR2*/TR1* TR0'
  77. STRING S_LSA     '(S_TDD+S_TTD+S_TAD+S_TBD)'
  78. STRING S_SET     '(S_LD_RG+S_LD_AT)'
  79.  
  80. ;----------------------------------- Boolean Equation Segment ------
  81. EQUATIONS
  82.  
  83. STATE
  84.  
  85. M_C2_0  = /K_C2_1*/K_C2_0    ;C2 Control State Definition
  86. M_C2_1  = /K_C2_1* K_C2_0
  87. M_C2_2  =  K_C2_1*/K_C2_0
  88. M_C2_3  =  K_C2_1* K_C2_0
  89.  
  90.  
  91. MOORE_MACHINE            ;Trace State Machine
  92.  
  93. M_C2_0 := TRACE -> M_C2_1
  94.         +-> M_C2_0;
  95.  
  96. M_C2_1 := TRACE -> M_C2_2
  97.         +-> M_C2_0;
  98.  
  99. M_C2_2 := TRACE -> M_C2_1;
  100.         +-> M_C2_3;
  101.  
  102. M_C2_3 := VCC -> M_C2_0;
  103.         +-> M_C2_0;
  104.  
  105. M_C2_0.OUTF = /TM_G_CS*/TM_G_OE*/TM_G_WE*/TM_G_ADDR_CK
  106.              */GM_G_CS*/GM_G_OE*/GM_G_WE*/GM_G_ADDR_CK
  107. M_C2_1.OUTF =  TM_G_CS* TM_G_OE*/TM_G_WE* TM_G_ADDR_CK
  108.              * GM_G_CS* GM_G_OE*/GM_G_WE* GM_G_ADDR_CK
  109. M_C2_2.OUTF =  TM_G_CS* TM_G_OE* TM_G_WE*/TM_G_ADDR_CK
  110.              * GM_G_CS* GM_G_OE* GM_G_WE*/GM_G_ADDR_CK
  111. M_C2_3.OUTF = /TM_G_CS*/TM_G_OE*/TM_G_WE*/TM_G_ADDR_CK
  112.              */GM_G_CS*/GM_G_OE*/GM_G_WE*/GM_G_ADDR_CK
  113. ;---------------------------- CONDITIONs Sub Segment ------------
  114.  
  115. CONDITIONS
  116.  
  117. TRACE =     S_LSA*(S_TDD*S_K3 + S_TTD*S_K2 + S_TAD*S_K3 + S_TBD*S_K3)
  118.  
  119.  
  120.