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- Path: sparky!uunet!olivea!sgigate!odin!twilight!zola!anchor!olson
- From: olson@anchor.esd.sgi.com (Dave Olson)
- Newsgroups: comp.sys.sgi
- Subject: Re: R4400 (was: Re: Multiprocessor Crimson?)
- Message-ID: <v6emgt0@zola.esd.sgi.com>
- Date: 22 Jan 93 08:24:00 GMT
- References: <3304@contex.contex.com> <v4fbv18@zola.esd.sgi.com> <1jkgn3INNsmh@spim.mti.sgi.com> <1993Jan21.044828.17595@ringer.cs.utsa.edu> <1993Jan21.104509.11830@cc.ic.ac.uk> <1jmokqINNh82@spim.mti.sgi.com> <C180v5.L6q@news.cso.uiuc.edu>
- Sender: news@zola.esd.sgi.com (Net News)
- Organization: Silicon Graphics, Inc. Mountain View, CA
- Lines: 20
-
- In <C180v5.L6q@news.cso.uiuc.edu> ercolessi@uimrl3.mrl.uiuc.edu (furio ercolessi) writes:
- | i know this is one of the questions which have no answer, or any answer,
- | because it's application-dependent, but *roughly*, what kind of improvement in
- | 64-bit floating point speed is expected from the R4400, with respect to the
- | R4000? +10%? +50%? +300%?
-
- IF they are both running at 50 MHz (i.e., only the cache size differences
- having an effect), then I'd expect it to be quite small for most programs.
- Of course, if you have lots of loops that fit in 16K, but not in 8
- (or data for those loops), it could be fairly substantial.
-
- If you are talking 75 MHz R4400 vs 50 MHz R4000, then I'd expect
- somewhat less than 50% for most code, since memory bandwidth
- will (on most implementations, anyway) remain the same. Of course
- the cache effects above could also come into play. The real answer
- is that you will have to try on code that you care about.
- --
- Let no one tell me that silence gives consent, | Dave Olson
- because whoever is silent dissents. | Silicon Graphics, Inc.
- Maria Isabel Barreno | olson@sgi.com
-