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- Path: sparky!uunet!usc!sdd.hp.com!ux1.cso.uiuc.edu!roundup.crhc.uiuc.edu!uiuc.edu!parkes
- From: parkes@uiuc.edu (Steven Parkes)
- Newsgroups: comp.sys.mentor
- Subject: Fabricating chips using 8.* tools and MOSIS
- Date: 21 Jan 1993 17:18:44 GMT
- Organization: Center for Reliable and High-Performance Computing
- University of Illinois
- Lines: 32
- Distribution: world
- Message-ID: <1jmltlINNjsk@roundup.crhc.uiuc.edu>
- Reply-To: parkes@uiuc.edu
- NNTP-Posting-Host: chicago.crhc.uiuc.edu
-
- We at the University of Illinois are looking into fabbing chips through
- MOSIS from designs generated using the 8.* ICstation toolset.
-
- There are a number of tasks to be accomplished; some we have done, others we are
- looking into now. I'd like to collect information and experiences from anyone
- who has fabbed (or even looked into _attempting_ to fab) chips through MOSIS
- from designs generated by the 8.* tools.
-
- I'll pass on a summary to comp.sys.mentor, if there are any, so please don't
- send `me too' requests.
-
- Particular points of interest are:
-
- 1) What technologies have you used (i.e. SCMOS and CMOSN at 1.2, 2, or 3
- micron) and where did you get the necessary process and rules files.
- 2) What, if any, standard cell libraries have you used (i.e. the NSA libraries,
- in either technology)
- 3) What applications have you used (i.e. da, qsim, ICgraph, ICrules, ICtrace,
- ICextract, CPFI, Quick*)
- 4) What kind of modeling did you use (i.e. digital, analog, quickpart, etc.)
- 5) What kind of simulation did you do (i.e. digital, analog, functional,
- timing etc.)
- 6) What other kinds of verification did you do (i.e. timing with or without
- technology files)
-
- If you have any other information, particularly information on show-stoppers,
- or other issues not mentioned here, please send it.
-
- steven parkes ---------------------------------------
- Center for Reliable and High-Performance Computing --
- University of Illinois --
- parkes@uiuc.edu -------------------------------------
-