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- Path: sparky!uunet!gatech!asuvax!ncar!news.miami.edu!umiami!tcwan
- From: tcwan@umiami.ir.miami.edu
- Newsgroups: comp.sys.mac.hardware
- Subject: Re: Registers (was 68060 for Macs)
- Message-ID: <1993Jan21.152311.14364@umiami.ir.miami.edu>
- Date: 21 Jan 93 15:23:11 EST
- References: <1993Jan17.065150.25462@wixer.cactus.org> <1993Jan17.192745.13494@netcom.com> <WAGNER.93Jan21091430@grace.math.uh.edu>
- Followup-To: comp.sys.mac.hardware
- Organization: Univ of Miami IR
- Lines: 44
-
- In article <WAGNER.93Jan21091430@grace.math.uh.edu>, wagner@grace.math.uh.edu (David Wagner) writes:
- > <1993Jan18.024452.20791@bilby.cs.uwa.edu.au> <mhk=Av+@engin.umich.edu>
- > <noah-200193075654@noah.apple.com>
- > NNTP-Posting-Host: grace.math.uh.edu
- > In-reply-to: noah@apple.com's message of 20 Jan 93 16:14:40 GMT
- >
- > It's nice to have all of these facts about size of registers,
- > data bus, clock speed, etc. But nobody had said anything
- > about numbers of registers. For example, the 68881 has
- > 8 extended-precision floating-point registers. By way of
- > comparison, the RS/6000 has 32 (double precision?) floating-
- > point registers. I believe the comparisons for integer and
- > address registers are similar, but I don't actually know.
- >
- > Clearly a processor can run faster if it can keep data in registers
- > rather than writing values out to memory and reading them back in
- > again when needed. Cache helps in this regard, but not quite as much
- > as registers. However binary compatibility for software demands that
- > processors have the same number of each type of register, or else only
- > the minimum number of registers will be used. Hence I would expect
- > that the 68060 will have the same register architecture as the
- > 68030/68882.
-
- Hmmm, seeing the comment about keeping data in registers -- there's an
- article in the latest Byte magazine about the Hobbit processor from
- AT&T. It doesn't use program addressible registers at all. It's a memory
- to memory architecture, compared to the more traditional register to memory
- architecture of the 68x000 and 80x86 chips.
-
- Of course, a very large cache will be needed to keep processing at the CPU
- speed.
-
-
- t.c.
- Grad student,
- Univ. of Miami, FL
-
- #This has nothing directly related to the 68060 discussion, but I'd thought
- that it's a neat idea :) [they didn't talk about this in my computer
- architecture class]
-
- >
- > David H. Wagner
- > You didn't hear it from me!
-