NetNews Usenet Archive 1993 #1/NN_1993_1.iso/spool/sci/electron/22028

Internet Message Format | 1993-01-05 | 3.7 KB

Path: sparky!uunet!pipex!bnr.co.uk!uknet!edcastle!dcs.ed.ac.uk!kc
From: [e-mail] (Kenneth Cameron)
Newsgroups: sci.electronics
Subject: Re: ASICs - what can you do with'em?
Message-ID: <[e-mail]>
Date: 5 Jan 93 21:56:21 GMT
References: <etxansk.726247208@garbod26>
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Reply-To: [e-mail] (Kenneth Cameron)
Organization: Laboratory for the Foundations of Computer Science, Edinburgh U
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In article <etxansk.726247208@garbod26> [e-mail] writes:
>
> I've read a little in magazines about ASICs. Since I'm only involved in
>software engineering at work, it's sometimes hard for me to tell the
>limitations of a certain technique by reading summaries etc.
>
> So, what can be done with ASICs?
>
> Is it possible to create more than just plain Y=f(X) logic with
>ASICs? Plain logic would probably be enough for doing a simple
>MMU or anything similar, but can something that involves (for instance)
>counters be implemented? Would it be possible to design a circuit that
>creates (video) hsync and vsync from a clock input with one single ASIC?

All depends what you mean by ASIC. From the description you give, it sounds
like you mean things like EPLDs, GALs etc. These are have a set of sum of
product blocks, with or without  latches on the outputs. They vary in size from
20 pin to 80+ pin. With 8 to 80 latches. They are very useful for doing the
F(x) stuff and special counters/state machines. Some are one time programmable
others can be erased using UV or electrically. Cost varies depending on price
from a pound (20 pin) to several tens. I would tend not to call these ASICs.
Programable logic (PLD) seems a better term.

The next step up is probably the Xilinx type field programmable logic. This
is an array of programmable cells which can be connected together using
routing channels which are also programmable. I'm not sure but I believe 20,000
gates is about the size that these things provide. Again I would class these
as programable logic. Intended to provide a prototyping mechanism for non
field programmable logic, which is what I more usually thing of as ASICs. These
have an array of gates. The function and routing of these is controlled by the
final few layers (metal). So these are 'programmed' during the manufacturing
stage. Because the first several layers (transistors) are fixed with only the
last few being changed for an application the cost is cheaper than full custom,
but only cost effective if large numbers are required (1000s?). The next step
up would be full custom. And if ever there was something that could be called
application specific these are them. The only way to do these in small quantites
(<100000) at a reasonable price is to use e-beam instead of masks and get
someone to subsidise you. I think the current price for academic designs in the
UK is about 30 ecu per square mm of design. For which you get a wafers worth.

> Are there other techniques that provide affordable single-chip custom
>design for the man on the street?

Assuming you don't want to talk about custom or semi-custom, the cheapest
with a high-ish density are the FPGAs. Although the start up cost for the
design enviroment is a few grand. Below that, the 20-24 pin PLD cost
a couple of pounds each. With a start up cost of 50 pounds+ (to several hunderd).
These are best suited to address decode and simple state machine apps.

Although silicon compilers provide the best fun if you can afford them :-)

> Thanks in advance,
> Anders Skelander
Your welcome.


--
[e-mail]                                         [e-mail]
4th Year Honours Student, Dept of Computer Science, The University of Edinburgh
Project: Acceleration of Constructive Solid Geometry Using a Custom VLSI Device