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- From: adiwan@quick.fox.cs.cmu.edu (Amer Diwan)
- Newsgroups: comp.arch
- Subject: Write buffer on DS5000
- Message-ID: <ADIWAN.93Jan11135137@QUICK.quick.fox.cs.cmu.edu>
- Date: 11 Jan 93 18:51:37 GMT
- Article-I.D.: QUICK.ADIWAN.93Jan11135137
- Sender: news@cs.cmu.edu (Usenet News System)
- Reply-To: adiwan@cs.cmu.edu
- Distribution: comp.arch comp.sys.mips
- Organization: School of Computer Science, CMU
- Lines: 26
- Nntp-Posting-Host: quick.fox.cs.cmu.edu
-
- I am collecting memory reference traces from ML programs compiled with SML/NJ
- compiler and running them through cache simulators (dinero/tycho). I am doing
- this on DECStations 5000/120 and DECStations 5000/200 running Mach. For
- me to be able to accurately evaluate the effects of memory access patterns on
- the running time of the programs, I need to have a detailed understanding of
- the write buffer behavior. I need answers to the following:
-
- 1. Latency of a write hit when the write buffer is empty
- 2. Latency of a write hit when the write buffer is full
- 3. Latency of a write miss when the write buffer is empty
- 4. Latency of a write miss when the write buffer is full
-
- The DS5000/200 specs. seem to answer at least 3: 13 cycles (CPU cache fill).
- What about the rest?
-
- Are there any trace driven simulators out there that take the write buffer
- into consideration?
-
- Thanks a lot.
- Amer
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