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- Xref: sparky comp.sys.amiga.programmer:17889 comp.sys.amiga.hardware:22139
- Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware
- Path: sparky!uunet!munnari.oz.au!cs.mu.OZ.AU!winikoff
- From: winikoff@cs.mu.OZ.AU (Michael David WINIKOFF)
- Subject: Re: CISC and RISC
- Message-ID: <9236416.13537@mulga.cs.mu.OZ.AU>
- Organization: Computer Science, University of Melbourne, Australia
- References: <amipb.04wr@amipb.gna.org> <37844@cbmvax.commodore.com> <Bz8FD1.Dxt@ns1.nodak.edu> <BzByvD.FA9@news.cs.andrews.edu> <1gnl0mINNpq2@crcnis1.unl.edu> <1992Dec16.185521.21232@ichips.intel.com> <jimomura.02k4@tndb.UUCP> <9235716.13776@mulga.cs.mu.OZ.AU> <jimomura.02ki@tndb.UUCP>
- Date: Tue, 29 Dec 1992 05:09:01 GMT
- Lines: 76
-
- jimomura@tndb.UUCP (Jim Omura) writes:
-
- >In article <9235716.13776@mulga.cs.mu.OZ.AU> winikoff@cs.mu.OZ.AU (Michael David WINIKOFF) writes:
- >>jimomura@tndb.UUCP (Jim Omura) writes:
- >>
- >>[Lots of quotes deleted]
- >>
-
- > Well, yes, I know that. That's why I raised the issue in *this*
- >discussion where nobody else has.
- Ack.
-
- >>In shared memory machines one relies heavily on caches to reduce the demand
- >>on the bus.
- >>
- >>Another solution to having multiple processors is to build distributes
- >>memory machines.
-
- > Let me repeat "there are going to be times where the various
- >busses are going to be the main bottleneck". This will be true
- >in spite of distributed memory and caching. Actually, I thought
- >I implied that fairly well.
- >:-)
-
- Yup, if these times don't occur that often though then you're fine.
-
- >>Essentially what (I think) you're saying is "we shouldn't use the fastest
- >>CPUs we can on a multiprocessor machines since they'll be tying up more
- >>bus bandwidth then slower processors"
-
- > That's close. To state it more accurately, we're reaching a
- >point where certain classes of applications which push designs
- >in various directions have significant representation in the market.
- >Considering all the design specification factors (user needs and
- >preferences, design costs, material costs and production costs),
- >better performance may be achieved where overall system architectures
- >are optimized towards certain applications. And some CPUs will
- >be better suited that others in this overall context. More
- >specifically, in some designs, super-scalar RISCs simply may not
- >give performance as good as CISC. Furthermore, there should be
-
- Sure - just leave out the cache :-)
-
- >advantages in designing CPUs with more of an eye on final applications
- >and working backwards through the overall system architecture
- >than there has been in the past. This may be happening in the
-
- Huh? Isn't this what the RISC approach is all about?
- [Ref. Computer architecture: a quantitative approach. Hennesy & Patterson]
-
- >Apple/IBM/Motorola project -- I don't know.
-
- Whoa! That's a mouthful. You sure you ain't a lawyer/politician/marketroid? :-)
-
- > I might also add that I doubt that we're close to seeing the
- >ultimate designs in any of these classes.
-
- I don't think there ever will be an "ultimate" design since the technology
- used to implement designs is continuously developing.
-
- > Incidentally, the latest word I have is that the physical signals
- >in the Apple/IBM/Motorola RISC are essentially 88000 signals, so
- >that might be a good reason to design the next generation Amigas
- >on 88000's.
-
- >...
-
- >--
-
- >Jim Omura, (416) 652-3880
- >'jimomura@lsuc'
- --
-
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